Chip package capable of reducing moisture penetration

Details Chip package capable of reducing moisture penetration Chip package capable of reducing moisture penetration

2001-11-19

2003-07-15

Talbott, David L. (Department: 2827)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified configuration

C257S784000, C257S786000, C174S251000, C174S255000

Reexamination Certificate

active

06593658

ABSTRACT:

FIELD OF THE INVENTION
The present invention generally relates to a semiconductor chip package in which at least a chip is attached to a chip carrier having at least a bonding finger and a plating-conduction-line formed thereon and connected with each other, and particularly to a chip package capable of minimizing erosion caused by moisture penetration through a plating-conduction-line.
BACKGROUND OF THE INVENTION
As shown in
FIG. 1
, for better connection of bonding wires
2
of a chip
1
to the bonding fingers
3
on a chip carrier
4
(a substrate for example), special material such as a thin gold layer must be plated on each bonding finger
3
of the chip carrier
4
, therefore plating-conduction-lines
7
must be formed on the chip carrier
4
so that each bonding finger
3
of the chip carrier
4
is connected with one of the plating-conduction-lines
7
, thereby electrical current can be conducted to each of the bonding fingers
3
respectively via one of the plating-conduction-lines
7
, in order to plate such special material on each of the bonding fingers
3
. The chip carrier
4
shown in
FIG. 1
is one of many obtained by dividing a large sheet of interim product, and has each plating-conduction-line
7
thereon cut, as a result of dividing the large sheet of interim product into many chip carriers, to have its first end on an edge such as
91
(or
93
) of the chip carrier
4
shown in
FIG. 1B
, where the edge
91
(or
93
) is the chip carrier's edge closest to the bonding finger
3
connected with the second end of the plating-conduction-line
7
. The second end of the plating-conduction-line
7
connects the bonding finger
3
via a first line
301
of the bonding finger
3
. The prior art in
FIG. 1
also comprises bonding wires
2
, ball pads
62
, at least a via
61
, an encapsulation layer
5
, and traces
8
connecting bonding finger
3
and ball pads
62
through at least a via
61
, and the chip carrier thereof includes edges
91
,
92
,
93
, and
94
. The length of the plating-conduction-line
7
spanning the first line
301
of the bonding finger
3
and the edge
91
always corresponds to the size of the gap
11
between the first line
301
of the bonding finger
3
and the edge
91
, edge
91
being the chip carrier's one edge which is closest to the first line
301
of the bonding finger
3
, as can be seen from FIG.
1
B. The length of the path for moisture to penetrate from edge
91
of the chip carrier
4
to the bonding finger
3
through plating-conduction-line
7
is the size of the gap
11
shown in
FIG. 1B. A
second line
302
of bonding finger
3
shown in
FIG. 1B
is for better comparison between the present invention and the prior art, as recited in the specification of the present invention.
Although a thin and small IC package can be achieved by conventional packaging technologies such as those for forming a CSP (chip scale package) based on wire bonding, the difference in size between the IC package and the chip therein is so small that the bonding finger
3
on the chip carrier (such as a substrate or a tape
4
shown in
FIG. 1
) in the package cannot be spaced from each edge (usually corresponding to the edge such as
91
or
93
of the chip carrier
4
shown in
FIG. 1
) of the package by a distance which is long enough to significantly reduce moisture penetration through a plating-conduction-line
7
spanning the bonding finger
3
and the edge
91
or
93
which is closest to the bonding finger
3
as shown in
FIG. 1B
, resulting in poor reliability of products. For an example in which a bonding finger is spaced from an edge (corresponding to an edge of a chip carrier) of a package by a distance no less than 0.165 mm, the layout of traces and bonding fingers becomes a problem particularly when packaging a memory chip which is usually relatively large. However, reducing the distance between the bonding finger and the edge of the package to solve the problem will inevitably lead to easier moisture penetration through a plating-conduction-line such as
7
of
FIG. 1B
in the prior art chip package, because a conventional semiconductor chip package, as can be seen from
FIG. 1B
, always has its plating-conduction-line
7
connecting a bonding finger
3
via the first line
301
of the bonding finger
3
and having an end on one of the chip carrier's edges which is closest to bonding finger
3
, such as the edge
91
(or
93
) in FIG.
1
B. The conventional plating-conduction-line
7
, as shown in
FIG. 1B
, always connects the bonding finger
3
in a direction perpendicular to the first line
301
of the bonding finger
3
. The first line
301
of the bonding finger
3
faces (i.e., approximately parallels) the edge
91
(or
93
) closest thereto.
Referring again to
FIG. 1
, in which a conventional chip package
10
comprises a chip carrier
4
such as a substrate or a tape to which a semiconductor chip
1
connecting a bonding wire
2
is attached, the chip carrier
4
including at least a bonding finger
3
formed thereon for connecting the bonding wire
2
and at least a trace
8
as well as a plating-conduction-line
7
both also formed thereon. The plating-conduction-line
7
has its first end on an edge
91
of chip carrier
4
and its second end connected to bonding finger
3
, and spans the gap
11
which is defined by edge
91
and a first line
301
of bonding finger
3
, the first line
301
facing edge
91
i.e., plating-conduction-line
7
is connected to bonding finger
3
in a direction perpendicular to first line
301
of bonding finger
3
, resulting in a shortest path for moisture to penetrate into conventional chip package
10
from edge
91
of chip carrier
4
along plating-conduction-line
7
in a direction as indicated by arrow
12
, leading to serious erosion of components inside conventional chip package
10
, particularly the erosion of bonding finger
3
therein, even though the bonding finger
3
, plating-conduction-line
7
, as well as the bonding wire
2
and chip
1
are covered by an encapsulation layer
5
. The present invention is therefore hereby disclosed to provide a scheme for resolving the problem.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a chip package having a better layout of traces, bonding finger, and plating-conduction-line, in order to increase the length of path for moisture to penetrate thereinto, thereby the erosion of components in the chip package can be significantly minimized.
The present invention is characterized by configuring a semiconductor chip package in such a way that a semiconductor chip package is attached to a chip carrier (such as a substrate, or a tape, or any material capable of supporting the chip and accommodating circuits) having thereon at least a bonding finger, and at least a plating-conduction-line with one end thereof on a selected edge of the chip carrier and being electrically conductive to the bonding finger through a path very different from those in a conventional semiconductor chip package, thereby the length of the path for moisture to reach the bonding finger or another components in the semiconductor chip package is significantly greater than that of a conventional semiconductor chip package, whereby moisture erosion can be effectively reduced. The plating-conduction-line is for conducting to the bonding finger the electrical current applied to its end on the selected edge of the chip carrier for plating special material such as gold on the bonding finger, in order to achieve better connection between the bonding wire and the bonding finger of the chip carrier.
One preferred aspect of the present invention is represented by a semiconductor chip package comprising:
at least a semiconductor chip;
at least a chip carrier having a front surface to which the chip is attached, and having a back surface, at least a via, and a plurality of edges;
at least a bonding finger formed on the front surface of the chip carrier to electrically connect the chip;
a metal pad (for example, a ball pad attached t

Affiliated with

Also associated with

Rating

Chip package capable of reducing moisture penetration does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Chip package capable of reducing moisture penetration, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Chip package capable of reducing moisture penetration will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3033022