Chemistry for liner removal in a dual damascene process

Details Chemistry for liner removal in a dual damascene process Chemistry for liner removal in a dual damascene process

2002-10-29

2004-10-26

Whitehead, Jr., Carl (Department: 2813)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S640000, C438S624000

Reexamination Certificate

active

06809028

ABSTRACT:

BACKGROUND OF THE INVENTION
(1) Field of the Invention
This invention relates to a method of fabrication used for semiconductor integrated circuit devices, and more specifically to fabricating dual damascene copper, in which trench/via liner removal from porous low-k dielectric, is performed using a new etch chemistry of CF
4
/H
2
, to etch SiN and SiC liners.
(2) Description of Related Art
In this section a description of related Prior Art background patents follows.
U.S. Pat. No. 6,255,226 B1 entitled “Optimized Metal Etch Process To Enable The Use of Aluminum Plugs” granted Jul. 3, 2001 to Zheng et al. shows a metal and barrier layer etch using a fluorine containing gas. A process for manufacturing a semiconductor device having metal interconnects reduces or eliminates the recessing of metal in the vias, particularly when the metal in the vias is aluminum or an aluminum alloy. By manipulating the etch chemistry so that the etch rates of the aluminum alloy, the surrounding barrier metals, and the dielectric are comparable, it is possible to perform the metal over etch without forming voids in the exposed portion of the via. By eliminating the voids, thinning of the vias due to the presence of recesses is minimized.
U.S. Pat. No. 6,228,775 B1 entitled “Plasma Etching Method Using Low Ionization Potential Gas” granted May 8, 2001 to Coburn et al. discloses a CF oxide etch. The etching method for forming an opening includes providing a substrate assembly having a surface and an oxide layer thereon. A patterned mask layer is provided over the oxide layer exposing a portion of the oxide layer. A plasma including one or more of CHF ions and CF ions and further including xenon or krypton ions is used to etch the oxide layer at the exposed portion to define the opening in the oxide layer while simultaneously depositing a polymeric residue on a surface defining the opening. The etching is continued until the opening in the oxide layer is selectively etched to the surface of the substrate assembly.
U.S. Pat. No. 6,159,862 entitled “Semiconductor Processing Method And System Using C
5
F
8
” granted Dec. 12, 2000 to Yamada et al. discloses a method and system for a CF dielectric etch. When processing oxides and dielectrics in a gas plasma processing system, C
5
F
8
is used in combination with a carrier gas (e.g., Ar) and one or more of CO and oxygen. When using a silicon nitride layer as an etch stop, effective etching is performed due to the selectivity of oxides versus silicon nitride. The method is used when etching down to self-aligning contacts and other layers. The method may be practiced with or without using an anti-reflective coating underneath the photoresist layer.
U.S. Pat. No. 6,265,779 B1 entitled “Method And Material For Integration Of Fluorine-Containing Low-K Dielectrics” granted Jul. 24, 2001 to Grill et al. reveals a dual damascene process with liners. Metal and insulator interconnect structures are described incorporating one or more layers of fluorinated dielectric insulation, one or more conductive wiring levels interconnected by vias and capping and/or liner materials to physically isolate the wiring levels and vias from the fluorinated dielectric such as fluorinated diamond like carbon which has a low dielectric constant. The invention overcomes the problem that can arise when fluorine in the fluorinated dielectric insulation reacts with other materials in the interconnect structure to produce unwanted fluorine-containing compounds that can interfere with the structure's mechanical integrity or interconnect function.
SUMMARY OF THE INVENTION
It is a general object of the present invention to provide an improved method for fabricating dual damascene copper, in which trench/via liner, or etch stop, removal from porous low-k dielectric, is performed using a new etch chemistry of CF
4
/H
2
, to etch SiN and SiC liners. Prior to this new process, convention liner etching produced the following deleterious results:
a) Cu re-deposition by sputtering, b) polymer deposits, and c) surface roughening of the porous low-k IMD dielectric. Process details are: CF
4
/H
2
based with approximate gas flow ratios of greater than 10 to 1, hydrogen to carbon tetra-fluoride. A nominal flow ratio of 300 to 20, hydrogen to carbon tetra-fluoride, or 15 to 1, was developed.
The key aspects of the present invention are as follows: a layer of photoresist is formed over an insulating layer, so as to expose trench opening, via openings and etch stop regions. The new etchant of the present invention, is applied in a reactive ion etch chamber for the sole purpose of removing the exposed etch stop layer, or trench/via liner, and thereby, exposing the underlying copper interconnection wiring. The trench/via liner, or exposed etch stop, is removed from a porous low-k dielectric environment, using a new etch chemistry of CF
4
/H
2
, to etch the SiN and SiC liners, which are used as dual damascene etch stops. Process details are: CF
4
/H
2
based with approximate gas flow ratios of greater than 10 to 1, hydrogen to carbon tetra-fluoride. A nominal gas flow ratio of 300 to 20, hydrogen gas to carbon tetra-fluoride gas, which reduces to a ratio of 15 to 1, was developed. The CF
4
/H
2
based, RIE, reactive ion etch process yields good etch stop removal, in a reducing atmosphere with HF generation, with smooth shiny copper without CuO, and a smooth intermetal dielectric surfaces, and that does not need any subsequent solvent processing steps. The present invention applies to porous low dielectric constant dielectric insulators with dielectric constants less than 2.5 selected from the group comprised of several Japanese company products, JSR: LKD-5109, 2 Dou, Xerogel, Trikon: Orion, and other porous, low dielectric constant insulators. The other applicable materials are comprised of low dielectric constant porous materials selected from the group comprised of: SiN, SiO, SOG, which is spun-on-glass, PE plasma enhanced TEOS, which is tetraethoxysilane, halogenated SiO, and fluorinated silicate glass. All the materials above are deposited by a chemical vapor deposition process or a spin-on process.
This invention has been summarized above and described with reference to the preferred embodiments. Some processing details have been omitted and are understood by those skilled in the art. More details of this invention are stated in the “DESCRIPTION OF THE PREFERRED EMBODIMENTS” section.


REFERENCES:
patent: 5310454 (1994-05-01), Ohiwa et al.
patent: 6333258 (2001-12-01), Miyata et al.
Thanawala et al, “Reduction in the Effective Dielectric Constant of Integrated Interconnect Structures through an All-Spin-on Strategy” http://www.advanced-polymers.com/star_center/technical_papers/reduction_in_effective_dielectric_constant.pdf.

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