Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-03-07
2003-05-13
Fourson, George (Department: 2823)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S493000, C438S763000, C438S938000
Reexamination Certificate
active
06562678
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention in general relates to the fabrication of layered superlattice materials, and more particularly to a chemical vapor deposition method for making thin films of layered superlattice materials, and to thin films of layered superlattice materials fabricated using such method.
2. Statement of the Problem
Ferroelectric compounds possess favorable characteristics for use in nonvolatile integrated circuit memories. See U.S. Pat. No. 5,046,043, issued Sep. 3, 1991, to Miller et al. A ferroelectric device, such as a capacitor, is useful as a nonvolatile memory when it possesses desired electronic characteristics, such as high residual polarization, good coercive field, high fatigue resistance, and low leakage current. Layered superlattice material oxides have been studied for use in integrated circuits. Layered superlattice materials exhibit characteristics in ferroelectric memories that are orders of magnitude superior to those of PZT and PLZT compounds.
U.S. Pat. No. 5,519,234, issued May 21, 1996, to Paz de Araujo et al., discloses that layered superlattice compounds, such as strontium bismuth tantalate (SBT), have excellent properties in ferroelectric applications as compared to the best prior materials and have high dielectric constants and low leakage currents. U.S. Pat. No. 5,434,102, issued Jul. 18, 1995, to Watanabe et al., and U.S. Pat. No. 5,468,684, issued Nov. 21, 1995, to Yoshimori et al., describe processes for integrating these materials into practical integrated circuits. Ferroelectric layered superlattice materials, like the metal oxides SrBi
2
Ta
2
O
9
(SBT) and SrBi
2
(Ta
1−x
Nb
x
)
2
O
9
(SBTN), where 0≦x≦1, are currently under development for use as capacitor dielectric in nonvolatile memory applications, such as in FeRAMs and nondestructible read-out ferroelectric FETs.
The layered superlattice materials currently being considered for use are metal oxides. Thin films of layered superlattice materials may be formed on a substrate using one of a number of techniques known in the art. Conventional deposition techniques include, for example, sputtering, sol-gel or metal organic deposition (“MOD”) techniques. The MOD techniques are preferred for various reasons, including stability of liquid precursor solutions, and good control of stoichiometry in the precursor streams and in the ferroelectric thin film. An MOD technique for depositing a thin film of superlattice material typically entails the decomposition of metal organic precursors to form a solid film of metal oxide compounds on an integrated circuit substrate, and the reaction and crystallization of the metal oxide compounds in the solid film to form the desired polycrystalline layered superlattice material. Formation of polycrystalline layered superlattice material is necessary in order to obtain desired ferroelectric polarizability. Reaction and crystallization to form polycrystalline ferroelectric layered superlattice material invariably requires one or more steps of heating the solid film.
A well-known category of techniques for depositing MOD precursors on integrated circuit substrates is chemical vapor deposition (“CVD”). CVD techniques are well-suited for small geometries and for achieving highly conformal structures in integrated circuits. In a CVD process, a gaseous stream containing metal organic precursor compounds is brought into contact with the heated surface of the substrate, which causes the metal organic precursor compounds to decompose at the substrate surface and form a solid film of metal-containing compounds.
In typical MOD-CVD fabrication of layered superlattice materials, reaction and crystallization of the deposited metal compounds to produce desired electronic properties requires heat treatments in oxygen gas at elevated temperatures. This heating is commonly referred to as annealing. Annealing at elevated temperature causes reaction of the deposited metal compounds and crystallization to form polycrystalline layered superlattice material. The annealing steps in the presence of oxygen are typically performed at a temperature in the range of 800° C. to 900° C. for 30 minutes to two hours. As a result of the presence of reactive oxygen at elevated temperatures, numerous defects, such as dangling bonds, are generated in the single crystal structure of the semiconductor substrate, leading to deterioration in its electronic characteristics. Annealing at elevated temperature for extended time may also damage other components of the integrated circuit, for example, diffusion barrier layers, which begin to degrade at temperatures of 700° C. and above.
The polarizability of ferroelectric layered superlattice material is affected by, among other factors, the grain size of the numerous crystal grains in the polycrystalline ferroelectric material. In the layered superlattice materials, it is believed that relatively large grain size enhances polarizability. Thin films of layered superlattice material formed using conventional CVD techniques, however, tend to have smaller grain size, resulting in decreased ferroelectric polarizability.
A persistent problem in dielectric and ferroelectric materials used in integrated circuits is charge dissipation and leakage current. It is believed that a significant part of leakage current travels along the grain boundaries of the crystal grains in polycrystalline dielectric and ferroelectric material.
SOLUTION
The present invention provides a chemical vapor deposition (“CVD”) method for fabricating ferroelectric layered superlattice materials in ferroelectric integrated circuits that minimizes the time of exposure to oxygen at elevated temperature, thereby reducing heat and oxidation damage. A CVD method in accordance with the invention produces relatively large grain size in the layered superlattice material, thereby enhancing ferroelectric polarizability. Further, a CVD method in accordance with the invention increases the path length of leakage charges in polycrystalline layered superlattice material, thereby reducing overall leakage current.
The layered superlattice materials, also referred to in the art as layered perovskite-like structures, are represented by the general formula:
A
1
w1
+a1
A
2
w2
+a2
. . . Aj
wj
+aj
S
1
x1
+s1
S
2
x2
+s2
. . . Sk
xk
+sk
B
1
y1
+b1
B
2
y2
+b2
. . . Bl
yl
+bl
Q
z
−q
, (1)
where A
1
, A
2
. . . Aj represent A-site elements in the perovskite-like structure, which may be elements such as strontium, calcium, barium, bismuth, lead, and others; S
1
, S
2
. . . Sk represents superlattice generator elements, which usually is bismuth, but can also be materials such as yttrium, scandium, lanthanum, antimony, chromium, thallium, and other elements with a valence of +3; B
1
, B
2
. . . B
1
represent B-site elements in the perovskite-like structure, which may be elements such as titanium, tantalum, hafnium, tungsten, niobium, zirconium, and other elements; and Q represents an anion, which generally is oxygen but may also be other elements, such as fluorine, chlorine and hybrids of these elements, such as the oxyfluorides, the oxychlorides, etc. The superscripts in Formula (1) indicate the valences of the respective elements. For example, if Q is O for oxygen, then q is 2. The subscripts indicate the number of moles of the material in a mole of the compound, or in terms of the unit cell, the number of atoms of the element, on the average, in the unit cell. The subscripts can be integer or fractional. That is, Formula (1) includes the cases where the unit cell may vary throughout the crystalline material, e.g. in SrBi
2
(Ta
0.75
N
0.25
)
2
O
9
, on the average, 75% of the B-sites are occupied by a tantalum atom and 25% of the B-sites are occupied by a niobium atom. If there is only one A-site element in the compound, then it is represented by the “A
1
” element and w
2
. . . wj all equal zero. If there is only one B-site element in the compound, then it is represented by the “B
1
” elemen
Paz de Araujo Carlos A.
Solayappan Narayan
Uchiyama Kiyoshi
Estrada Michelle
Fourson George
Patton & Boggs LLP
Symetrix Corporation
LandOfFree
Chemical vapor deposition process for fabricating layered... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Chemical vapor deposition process for fabricating layered..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Chemical vapor deposition process for fabricating layered... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3024355