Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Patent
1997-10-20
1999-12-14
Niebling, John F.
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
438629, 438633, 438648, 438656, 438643, 438645, 438653, 438669, 438672, 438685, 438687, 438692, 438693, 106 3, 106 11, 51309, H01L 100
Patent
active
060017309
ABSTRACT:
A method for forming a copper interconnect on an integrated circuit (IC) begins by forming a dielectric layer (20) having an opening. A tantalum-based barrier layer (21), such as TaN or TaSiN, is formed within the opening in the layer (20). A copper layer (22) is formed over the barrier layer (21). A first CMP process is used to polish the copper (22) to expose portions of the barrier (21). A second CMP process which is different from the first CMP process is then used to polish exposed portions of the layer (21) faster than the dielectric layer (20) or the copper layer (22). After this two-step CMP process, a copper interconnect having a tantalum-based barrier is formed across the integrated circuit substrate (12).
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J.M.Steigerwald et al., "Mat. Res. Soc. Symp. Proc.," vol. 337, 1994, Method of Chemica Mechanical Polishing Predominantly Copper Containing Metal Layers in Semiconductor Processing, pp. 133-138.
Bajaj Rajeev
Das Sanjit
Farkas Janos
Freeman Melissa
Watts David K.
Motorola Inc.
Niebling John F.
Witek Keith E.
Zarneke David A.
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