Charge-trapping memory device

Details Charge-trapping memory device Charge-trapping memory device

2006-12-05

2006-12-05

Quach, T. N. (Department: 2826)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S287000

Reexamination Certificate

active

07144776

ABSTRACT:
An oxidized region is arranged between a substrate of semiconductor material and a nitride liner, which covers wordline stacks of a memory cell array and intermediate areas of the substrate, and is provided to separate the nitride liner both from the substrate and from a memory layer sequence of dielectric materials that is provided for charge-trapping. The nitride liner is used as an etching stop layer in the formation of sidewall spacers used in a peripheral area to produce source/drain junctions of transistors of the addressing circuitry.

REFERENCES:
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patent: 5966603 (1999-10-01), Eitan
patent: 6011725 (2000-01-01), Eitan
patent: 6426247 (2002-07-01), Divakaruni et al.
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patent: 6913987 (2005-07-01), Haufe et al.
patent: 7041545 (2006-05-01), Willer
patent: 2003/0205727 (2003-11-01), Shin et al.
Eitan, B, et al., “NROM: A Novel Localized Trapping, 2-Bit Nonvolatile Memory Cell,” IEEE Electron Device Letters, vol. 21, No. 11, Nov. 2000, pp. 543-545.

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