Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-02-07
2002-03-26
Everhart, Caridad L. (Department: 2825)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S221000, C438S223000, C438S224000, C438S227000, C438S231000, C438S298000, C438S420000, C438S451000, C438S529000, C438S919000, C438S526000, C257S369000, C257S374000
Reexamination Certificate
active
06362035
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The invention relates to processes for the manufacture of semiconductor devices and more particularly to processes related to the formation of CMOS (complimentary metal oxide silicon) integrated circuits.
(2) Background of the Invention and Description or previous art
Integrated circuits(ICs) are manufactured by first forming discrete semiconductor devices within the surface of silicon wafers. A multi-level metallurgical interconnection network is then formed over the devices contacting their active elements and wiring them together to create the desired circuits. The most widely used semiconductor device is the familiar MOSFET (metal oxide field effect transistor). Both n- and p-channel MOSFETs are used in most integrated circuits and in many instances the two types are used together in a complimentary mode. This technology is referred to as CMOS (complimentary MOS) technology and, because of its low operating current requirements, is one of the most widely used circuit applications.
In order to have these devices essentially side-by-side on the chip, each is formed on a silicon wafer substrate, in a well of a conductivity type opposite to that of the channel type. Thus, n- and p-type wells must first be formed in the silicon surface to accommodate each of the devices. A discussion of twin-well or twin-tub CMOS technology may be found in Wolf, S., “Silicon Processing for the VLSI Era”, Vol.2, Lattice Press, Sunset Beach, Calif., (1990), p387ff.
On the silicon surface, a field isolation provides insulation between active elements of two adjacent devices. When the spacing between the devices becomes small, an interaction between two adjacent CMOS structures occurs beneath the field isolation. This interaction is commonly referred to as punchthrough. In order to prevent punchthrough a channel-stop or anti-punchthrough implant of higher dopant concentration than the well, is placed beneath the field isolation. Unfortunately, this increases the junction capacitance of the devices and consequently degrades circuit performance. By making the field isolation deeper and placing the channel stop implant deeper accordingly, the junction capacitance is improved. However, in integrated circuit processes where the field isolation is angled, such as in LOCOS (local oxidation of silicon) isolation or in wet etched recessed trench isolation, the trench angle limits the lateral spacing of the devices. Incorporating a deeper trench, therefore, necessitates a wider spacing with a consequent loss of circuit density. It would therefore be useful to have an improved channel stop which would provide a high degree of punchthrough protection with minimal sacrifice of junction capacitance. The present invention provides a method for forming such a channel stop. The method taught by the present invention is also applicable for integrated circuits with STI (shallow trench isolation).
Manning, U.S. Pat. No. 5,843,814 forms a BiCMOS, an integrated circuit having both n- and p-channel MOSFETs and bipolar transistors. The patterned boron implant which forms the base of the bipolar transistor also places a channel stop region beneath the field isolation adjacent to the n-channel device. The n-channel device is built directly in the p-type substrate, rather than in a p-well. Borland, U.S. Pat. No. 5,821,589, and U.S. Pat. No. 5,814,866 places a blanket, very deep, p-type buried layer beneath both n- and p-wells by using a 2MeV boron implant. The technique, involving multiple implants, provides a boron distribution under the field oxide connecting to the buried layer. This vertical p-type pillar isolation prevents lateral interaction of parasitic devices known as latch-up. Borland, U.S. Pat No. 5,501,993 shows a method for surrounding a well of one type with one of the opposite type to prevent latch-up.
Mehrad, U.S. Pat. No. 5,604,150 shows a supplemental high energy boron channel stop implanted into a p-well after the field oxide is grown. The high energy implant prevents the occurrence of an n-skin under the field oxide which results from the combined effects of boron depletion and phosphorous accumulation during the field oxidation. The supplemental high energy channel stop is directly under the field oxide but is deeper under the active areas. Lowery, et. al., U.S. No. 5,252,504 implants a boron channel stop, using the field oxide mask before the field oxide is grown by LOCOS. The nitride field oxide mask blocks the implant over the active regions. Lee, U.S. Pat. No. 4,839,301 and U.S. Pat. No. 5,073,509 show methods for forming p-type channel stops for CMOS structures by using the LOCOS field oxide mask to protect the active areas. The boron ion implants are performed prior to LOCOS field oxidation.
In instances wherein the channel stop implant precedes a LOCOS field oxidation, the implant is shallow, being just below the surface of the silicon in the field regions. During the field oxidation the boron is driven advantageously deeper, ahead of the oxidation front. It is however depleted at the oxidation front. When the channel stop implant is delivered after the field oxide is grown, as in Mehrad, the boron is implanted deeper in the active regions than under the field oxide because the LOCOS field oxide thickness is about twice that of the silicon consumed by the oxidation. In addition boron depletion under the field oxide is overcome or avoided.
While in Mehrad, the increased depth of the boron field implant (channel stop) will advantageously lower the junction capacitance between a n+to device element in the p-well, the effect of the same implant in a corresponding n-well of a CMOS pair would be disadvantageous because a higher n-well implant dosage would be required to sufficiently overcompensate the p-type field implant and thereby cause an imbalance in CMOS performance. Thus, in the framework of Mehrad, a blanket channel stop implant is only suitable where the circuit devices are all of the same type.
SUMMARY OF THE INVENTION
It is an object of this invention to provide an improved method for forming a channel stop region in a twin-well CMOS integrated circuit with reduced junction capacitance without sacrificing anti-punchthough effectiveness.
It is another object of this invention to provide an improved method for forming a channel stop region in a twin-well CMOS integrated circuit without requiring photolithographic masking.
It is yet another object of this invention to provide a method for improving the isolation performance of a twin-well CMOS integrated circuit.
It is still another object of this invention to provide a method for forming a blanket boron field implant which may be overcompensated in an n-well of a CMOS structure without degrading balanced CMOS device performance.
These objects are accomplished by ion implanting a boron channel stop layer after the field isolation has been formed and the surface of the wafer planarized. The dosage and the energy of the implantation is chosen so as to place the centroid of the implant just below the bottom of the field isolation, assuring that the entire region of the channel stop abutting the base of the field isolation over the p-well remains strongly p-type, while at the same low enough so that the dosage of the n-well implantation is sufficient to over compensate the p-dopant in the n-well.
REFERENCES:
patent: 4710477 (1987-12-01), Chen
patent: 4839301 (1989-06-01), Lee
patent: 5073509 (1991-12-01), Lee
patent: 5141882 (1992-08-01), Komori
patent: 5212100 (1993-05-01), Groves et al.
patent: 5252504 (1993-10-01), Lowrey
patent: 5478759 (1995-12-01), Mametrani et al.
patent: 5501993 (1996-03-01), Borland
patent: 5573963 (1996-11-01), Sung
patent: 5604150 (1997-02-01), Mehrad
patent: 5795803 (1998-08-01), Takamura et al.
patent: 5814866 (1998-09-01), Borland
patent: 5821589 (1998-10-01), Borland
patent: 5985743 (1998-11-01), Gardner
patent: 5843814 (1998-12-01), Manning
patent: 5929493 (1999-07-01), Wu
patent: 5930617 (1999-07-01), Wu
patent: 6136636 (2000-10-01), Wu
patent: 6294416 (
Chen Shui-Hung
Lee Jian-Hsing
Lin Hsien-Chin
Shih Jiaw-Ren
Ackerman Stephen B.
Everhart Caridad L.
Keshavan Belur
Saile George O.
Taiwan Semiconductor Manufacturing Company
LandOfFree
Channel stop ion implantation method for CMOS integrated... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Channel stop ion implantation method for CMOS integrated..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Channel stop ion implantation method for CMOS integrated... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2819427