Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
2000-02-04
2004-09-21
Kunemund, Robert (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C438S689000, C438S709000, C438S711000, C438S712000, C438S713000, C438S714000
Reexamination Certificate
active
06794298
ABSTRACT:
TECHNICAL FIELD
The present invention relates to high density, multi-metal layer semiconductor device with reliable interconnection patterns. The present invention has particular applicability in manufacturing ultra large scale integration multi-metal layer semiconductor devices with a design rule of about 0.15 micron and under, e.g., about 0.12 micron and under.
BACKGROUND ART
The escalating demands for high density and performance associated with ultra large scale integration semiconductor devices require a design rule of about 0.15 micron and under, such as about 0.12 micron and under, increased transistor and circuit speeds, high reliability and increased manufacturing throughput. The reduction of design rules to about 0.15 micron and under challenges the limitations of conventional interconnection technology, including conventional photolithographic, etching and deposition techniques.
Conventional semiconductor devices typically comprise a semiconductor substrate, typically doped monocrystalline silicon, and a plurality of sequentially formed inter-layer dielectrics and patterned metal layers. An integrated circuit is formed containing a plurality of conductive patterns comprising conductive lines separated by interwiring spacings, and a plurality of interconnect lines, such as bus lines, bit lines, word lines and logic interconnect lines. Typically, the conductive patterns on different layers, i.e., upper and lower layers, are electrically connected by a conductive plug filling a via opening, while a conductive plug filling a contact opening establishes electrical contact with an active region on a semiconductor substrate, such as a source/drain region. Conductive lines are formed in trenches which typically extend substantially horizontal with respect to the semiconductor substrate. Semiconductor “chips” comprising five or more levels of metallization are becoming more prevalent as device geometries shrink into the deep submicron range.
A conductive plug filling a via opening is typically formed by depositing an inter-layer dielectric on a patterned conductive (metal) layer comprising at least one metal feature, forming an opening in the inter-layer dielectric by conventional photolithographic and etching techniques, and filling the opening with a conductive material, such as tungsten (W). Excess conductive material on the surface of the inter-layer dielectric is removed by chemical-mechanical polishing (CMP). One such method is known as damascene and basically involves the formation of an opening which is filled in with a metal. Dual damascene techniques involve the formation of an opening comprising a lower contact or via opening section in communication with an upper trench opening section, which opening is filled with a conductive material, typically a metal, to simultaneously form a conductive plug in electrical contact with a conductive line.
The conventional practice of forming a landing pad completely enclosing the bottom surface of a contact or via utilizes a significant amount of precious real estate on a semiconductor ship which is antithetic to escalating demands for high density. In addition, it is extremely difficult to voidlessly fill through-holes having such reduced dimensions because of the extremely high aspect ratio, i.e., height/width of the through-hole opening. Accordingly, conventional remedial techniques comprise purposely widening the diameter of the through-hole to decrease the aspect ratio. As a result, misalignment occurs wherein the bottom surface of the conductive via is not completely enclosed by the underlying metal feature. This type of via is called a “borderless via”, which also conserves chip real estate.
High performance microprocessor applications require rapid speed of semiconductor circuitry. The speed of semiconductor circuitry varies inversely with the resistance and capacitance of the interconnection pattern. As integrated circuits become more complex and feature sizes and spacings become smaller, the integrated circuit speed becomes less dependent upon the transistor itself and more dependent upon the interconnection pattern. Miniaturization demands long interconnects having small contacts and small cross-sections. As the length of metal interconnects increases and cross-sectional areas and distances between interconnects decrease, the resistance capacitance (RC) delay caused by the interconnect wiring increases. If the interconnection node is routed over a considerable distance, e.g., hundreds of microns or more, as in submicron technologies, the interconnection capacitance limits the circuit node capacitance loading and, hence, the circuit speed. As design rules are reduced to about 0.15 micron and below, the rejection rate due to integrated circuit speed delays severely limits production throughput and significantly increases manufacturing costs. Moreover, as line widths decrease, electrical conductivity and electromigration resistance become increasingly important.
As device geometries shrink and functional density increases, it becomes increasingly imperative to reduce the capacitance between metal lines. Line-to-line capacitance can build up to a point where delay time and cross talk may hinder device performance. Reducing the capacitance within multi-level metallization systems will reduce the RC constant, cross talk voltage, and power dissipation between the lines.
One way to increase the speed of semiconductor circuitry is to reduce the resistance of a conductive pattern. Conventional metallization patterns are typically formed by depositing a layer of conductive material, notable aluminum or an alloy thereof, and etching, or by damascene techniques where trenches are formed in dielectric layers and filled with conductive material. The use of metals having a lower resistivity than aluminum, such as copper, engenders various problems which limit their utility. For example, copper readily diffuses through silicon dioxide, the typical dielectric material employed in the manufacture of semiconductor devices, and adversely affects the devices. In addition, copper does not form a passivation film, as does aluminum. Hence, a separate passivation layer is required to protect copper from corrosion.
The dielectric constant of materials currently employed in the manufacture of semiconductor devices for an inter-layer dielectric (ILD) spans from about 3.5 for dense silicon dioxide to over 8 for deposited silicon nitride and spin-on glass. Prior attempts have been made to reduce the interconnect capacitance and, hence, increase the integrated circuit speed, by developing dielectric materials having a lower dielectric constant than that of silicon dioxide. New materials having low dielectric constants, such as low dielectric constant polymers, e.g., methyl silsesquioxane (MSQ) and hydrogen silsesquioxane (HSQ), teflon, aerogels and porous polymers have been developed. There has been some use of certain polyimide materials for ILDs which have a dielectric constant slightly below 3.0.
Low dielectric constant (low-k) polymers, such as HSQ, offer many advantages for use in interconnect patterns. HSQ is relatively carbon free, thereby avoiding poison via problems. Moreover, due to the virtual absence of carbon, it is not necessary to etch back HSQ below the upper surface of the metal lines to avoid shorting. In addition, HSQ exhibits excellent planarity and is capable of gap filling interwiring spacings less than 0.15 microns employing conventional spin-on equipment. HSQ undergoes a melting phase at approximately 200° C., but does not convert to the high dielectric constant glass phase until reaching temperatures of about 400° C. for intermetal applications and about 700° C. to about 800° C. for premetal applications.
However, low-k polymers, such as MSQ and HSQ, are susceptible to degradation during processing leading to various problems, such as voids, particularly when used as gap fill layers or ILDs during contact or via formations, particularly when forming borderless vias. For example, when forming a conventional contact or via
Rakhshandehroo Mohammad R.
Shields Jeffrey A.
You Lu
Advanced Micro Devices , Inc.
Kunemund Robert
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