Cavity down HBGA package structure

Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Flip chip

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Details

257706, 257707, H01L 2348, H01L 2352, H01L 2940

Patent

active

059106867

ABSTRACT:
An integrated-circuit die is attached to the top interior surface of a die-cavity formed in the underside of a heat spreader. The other side of the integrated circuit die has a number of wire-bonding pads formed thereupon. A plurality of bonding-wire loops at least some of which are completely contained within the die-cavity to allow the part of the encapsulation or lid to be as thin as possible, while still covering the bonding wires. A first portion of a insulated tape layer covers the lower outside surface of the die-carrier/heat spreader and another portion of the insulated tape layer extends inside of the die-cavity and has a number of wire-bonding sites formed thereupon. A plurality of bonding-wire loops are bonded to one of the wire-bonding pads formed on the integrated-circuit die and the wire-bonding sites formed on the insulated tape layer. Conductive traces connect the wire-bonding sites located inside of the die-cavity to respective selective solderable areas arranged in a grid pattern for receipt of solder balls. Encapsulation material or a ceramic or metal lid cover and seal the integrated-circuit die and the bonding wires in the die-cavity. The wire-bonding sites formed in the die-cavity are adhesively fixed to the top interior surface of the die-cavity. To increase bonding-wire density, the wire-bonding sites and the wire-bonding pads on the integrated-circuit die are arranged in two or more rows. Other wire-bonding sites are optionally formed outside of the die-cavity.

REFERENCES:
patent: 5530282 (1996-06-01), Tsuji
patent: 5661086 (1997-08-01), Nakashima et al.
patent: 5668405 (1997-09-01), Yamashita
patent: 5731631 (1998-03-01), Yama et al.
patent: 5834839 (1998-11-01), Mertol
patent: 5847935 (1998-12-01), Thaler et al.

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