Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2002-05-10
2003-12-09
Lee, Eddie (Department: 2815)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S244000, C438S253000, C438S387000, C438S396000
Reexamination Certificate
active
06660580
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a capacitor of an integrated circuit device and a method of manufacturing the same. More particularly, the present invention relates to a metal-insulator-metal capacitor of a semiconductor memory cell such as a dynamic random access memory cell, and a method of manufacturing the same, in which oxidation of a contact plug during deposition of a dielectric material having a high dielectric constant to form a dielectric layer is prevented.
2. Description of the Related Art
As a degree of integration of a semiconductor memory device, such as a DRAM cell increases, it becomes more difficult to obtain a sufficient capacitance due to a resulting decrease in size of individual memory cells. Recently, various efforts have been made to obtain a sufficient capacitance from a limited cell area.
There are typically two methods to increase a cell capacitance. A first method is to use a material having a high dielectric constant as a dielectric layer of the capacitor. A second method is to increase an effective area of the cell using a hemisphere silicon grain (HSG) growing method.
As for the material having a high dielectric constant, a metal oxide layer comprised of Ta
2
O
5
, TaOxNy, Al
2
O
3
, (Ba, Sr)TiO
3
[BST], SrTiO
3
[ST], Pb(Zi, Ti)O
3
[PLZT], SBT, or like, is used instead of a silicon oxide layer or a nitride layer.
Even though the dielectric layer is formed by depositing Ta
2
O
5
on a semiconductor substrate by a chemical vapor deposition (CVD) method, an oxygen vacancy where an oxygen bonding is absent is inevitably present in the dielectric layer. Therefore, a UV O
3
treatment is typically performed to supplement the oxygen vacancy during the CVD process. Furthermore, the dielectric layer is crystallized by means of a heat treatment in an oxygen atmosphere to increase a dielectric constant after performing the deposition.
A storage node is oxidized through a reaction with oxygen when the dielectric layer comprised of Ta
2
O
5
is subjected to the heat treatment in an oxygen atmosphere during or after the deposition thereof. Formation of an oxide layer through this oxidation process increases the thickness of the dielectric layer of the capacitor, thereby decreasing the dielectric constant, which results in a reduction in capacitance of the capacitor of the semiconductor memory cell.
Since the use of an existing polysilicon electrode is limited, a novel material for formation of an electrode and a novel structure of the electrode are required. As platinum (Pt) has a high reactivity to silicon, when platinum is used for formation of the electrode, a barrier layer is needed to insulate the platinum electrode from a contact plug comprised of polysilicon. Typically, titanium nitride or tantalum nitride is used as the barrier layer.
However, during or after deposition of a layer to form a lower electrode or a dielectric layer, a heat treatment is performed in an oxygen atmosphere to crystallize the lower electrode layer or the dielectric layer. During this heat treatment, oxygen diffuses along a boundary surface between a barrier layer and an insulation layer to reach a contact plug, resulting in oxidation of a surface portion of the contact plug. The oxidation of the contact plug decreases the capacitance of the capacitor of the semiconductor memory cell.
Hereinafter, a conventional capacitor of an integrated circuit device will be described.
FIG. 1
illustrates a sectional view showing a conventional concave type of a metal-insulator-metal capacitor of an integrated circuit device.
FIG. 2
illustrates a sectional view showing a conventional convex type of a metal-insulator-metal capacitor of an integrated circuit device.
The concave type of the metal-insulator-metal capacitor of the integrated circuit device is formed in such a manner that a first insulation layer
12
is formed on a semiconductor substrate
10
and a contact plug
14
is formed in the first insulation layer
12
. A diffusion barrier layer
16
comprised of a nitride material and a second insulation layer
18
are sequentially deposited on the contact plug
14
. A through hole
20
is formed in the second insulation layer
18
and through the diffusion barrier layer
16
. A barrier layer
22
, a lower electrode layer
24
, a dielectric layer
26
and an upper electrode layer
28
are subsequently formed in the through hole along a surface profile of the through hole
20
.
The convex type of the metal-insulator-metal capacitor of the integrated circuit device is formed in such a manner that a first insulation layer
112
is formed on a semiconductor substrate
110
and a contact plug
114
is formed in the first insulation layer
112
. A barrier layer
122
and a thick lower electrode layer
124
are integrated and subsequently formed on the contact plug
114
.
Then, the barrier layer
122
and the lower electrode layer
124
are patterned by a photolithography so that each node is defined. Subsequently, a dielectric layer
126
and an upper electrode layer
128
are sequentially stacked on the lower electrode
124
.
In
FIGS. 1 and 2
, when the dielectric layers
26
and
126
are crystallized under an oxygen atmosphere, oxygen diffuses toward an upper portion of the contact plugs
14
and
114
along oxygen diffusion pathways
30
and
130
on a boundary surface between the barrier layers
22
and
122
and the insulation layers
12
and
112
. As a result, the contact plugs
14
and
114
formed of polysilicon make contact with oxygen at the upper portion thereof to be oxidized and converted into silicon oxide layers
32
and
132
, which act as an insulator. This increases a contact resistance between the lower electrode and the plug of the capacitor thereby decreasing reliability of the cell capacitor.
From
FIGS. 1 and 2
, it may be noted that since the convex type of the capacitor of the integrated circuit device has a shorter oxygen diffusion pathway
130
than the oxygen diffusion pathway
30
of the concave type of the capacitor of the integrated circuit device, the convex type of the capacitor of the integrated circuit device has a weaker structure. Accordingly, the plug of the convex type capacitor is more easily oxidized due to the diffusion of oxygen than the concave type capacitor of the integrated circuit device.
Furthermore, in the concave type metal-insulator-metal capacitor, the nitride layer
16
is disposed between the first insulation layer
12
and the second insulation layer
18
to prevent the diffusion of oxygen.
However, although the nitride layer acts to substantially reduce the oxidation of the upper portion of the plug, the nitride layer cannot completely prevent oxidation of the plug.
That is, it is difficult to prevent oxidation of the plug because the nitride layer as the diffusion barrier layer is not sufficiently dense, and a distance between the nitride layer and the upper portion of the plug is very short.
SUMMARY OF THE INVENTION
In order to solve the aforementioned problems, it is a feature of an embodiment of the present invention to provide a capacitor of an integrated circuit device capable of preventing oxidation of a contact plug, in which a diffusion barrier layer is formed in a pathway through which oxygen diffuses.
It is another feature of an embodiment of the present invention to provide an advantageous method of manufacturing the capacitor of an integrated circuit device described above.
In order to provide the first feature of the present invention, a capacitor of an integrated circuit device according to a first embodiment of the present invention is provided. A first insulation layer is formed on a semiconductor substrate, and a buried contact hole is formed therein. A buried contact plug is formed in the buried contact hole for filling a portion of the buried contact hole to a predetermined height. A diffusion barrier spacer is formed on the buried contact plug and on an inner side surface of an upper portion of the buried contact hole. On the f
Lee Eddie
Lee & Sterba, P.C.
Richards N. Drew
Samsung Electronics Co,. Ltd.
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