Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2008-03-18
2008-03-18
Elmore, Stephen C. (Department: 2185)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S145000, C711S154000, C712S238000, C712S239000
Reexamination Certificate
active
11114464
ABSTRACT:
A cache system has a branch target address cache, including a storage unit for storing branch target address cache (BTAC) access bits each corresponding to cache lines of an instruction cache. The BTAC access bits represent a presence of a branch instruction on the next cache line of a cache line corresponding to the instruction cache. The BTAC is selectively accessed in accordance with values of the BTAC access bits corresponding to I'th (I is a positive integer) cache lines presently accessed in the instruction cache.
REFERENCES:
patent: 5822576 (1998-10-01), Dinkjian et al.
patent: 5848269 (1998-12-01), Hara
patent: 5933850 (1999-08-01), Kumar et al.
patent: 6247097 (2001-06-01), Sinharoy
patent: 6253316 (2001-06-01), Tran et al.
patent: 2000-132391 (2000-05-01), None
patent: 10-0276138 (2000-09-01), None
Elmore Stephen C.
Mills & Onello LLP
Samsung Electronics Co,. Ltd.
LandOfFree
Cache system having branch target address cache does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Cache system having branch target address cache, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Cache system having branch target address cache will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3936026