Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-10-12
2003-07-08
Thomas, Tom (Department: 2811)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S244000, C438S253000, C438S622000
Reexamination Certificate
active
06589837
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a method for making the semiconductor device, and more particularly to a buried contact hole structure.
2. Description of the Related Art
Recently, the design rule of highly integrated semiconductor memory devices has been reduced from about 1 &mgr;m, i.e., the level of mega-bit grade DRAMs, to about 0.15 &mgr;m, i.e., the level of giga-bit grade DRAMs. Due to such a reduction in a design rule, the size of a contact hole, which forms an electrical contact with a silicon substrate, has also been reduced. Because such a reduction in design rule in a vertical direction has been implemented using a three-dimensional capacitor structure, an aspect ratio has also been increased. However, the reduction in the diameter of the contact hole and the increased aspect ratio burdens a subsequent photolithography process. The design rule is one of the factors associated with so-called process limitations. In particular, the alignment tolerance in the deep submicron design rule is an important factor for determining a fatal failure of devices.
Development efforts associated with DRAM techniques have focused on an increase in capacitance within a limited unit area. As a result, capacitor structures have been developed from a planar cell structure to a stacked or trenched structure. Also, the stacked capacitor structure has been further developed to provide an increased effective capacitor area, e.g., using a cylinder or fin type capacitor structure.
Similar capacitor structure developments have been made in terms of the process sequence. That is, capacitor structures have been developed from a capacitor-under-bit-line (CUB) structure, in which capacitors are formed prior to the formation of bit lines, to a capacitor-over-bit-line (COB) structure, in which capacitors are formed after the formation of bit lines. In accordance with the COB structure, capacitors can be formed irrespective of the process margin given for a bit line process because the capacitors are formed after the formation of bit lines. Accordingly, the COB structure significantly increase capacitance within a limited cell area, as compared to the CUB structure. In other words, because the capacitors are formed over bit lines in the COB structure, storage node electrodes can have a maximum size determined by a limit given for the photolithography process, thereby providing a large capacitance.
However, such a COB structure increase the aspect ratio of a buried contact hole adapted to connect a storage node electrode to an active region of the device. Also, the misalignment margin between the storage node electrode and buried contact hole is reduced. In order to increase the misalignment margin between the storage node electrode and buried contact hole, it is necessary to reduce the buried contact hole to a minimum size, but it is also necessary to prevent the buried contact hole from being not-open, while increasing the storage node to a maximum size without causing the storage node to be bridged with neighboring storage nodes.
FIGS. 1
to
4
are cross-sectional views illustrating a conventional method for forming buried contacts in a semiconductor device.
Referring to
FIG. 1
, over a semiconductor substrate
10
, a field oxide film
11
is formed using a well-known device isolation process, thereby defining, within the substrate
10
, an active region and a field region. Thereafter, MOS transistors (not shown), each of which has a word line, and source and drain regions, are formed on the substrate
10
.
Subsequently, an oxide film (not shown) is formed over the resulting structure obtained after the formation of the MOS transistors. The oxide film is then etched using a photoetching process, thereby forming contact holes (not shown) through which the source and drain regions of the MOS transistors are exposed. Over the resulting structure, a doped-polysilicon layer is deposited, and then the resulting structure is patterned to form landing pads
12
contacting respective source and drain regions. The landing pads
12
serve to reduce the aspect ratios of bit line contact holes and buried contact holes to be formed in a subsequent process.
A first interlayer insulating layer
13
is then formed over the resulting structure obtained after the formation of the landing pads
12
. The first interlayer insulating layer
13
is etched using a photoetching process, thereby forming bit line contact holes (not shown) through which the landing pads
12
formed on the respective drain regions are exposed. Thereafter, a doped polysilicon layer
14
, a tungsten silicide layer
15
, and a capping layer (not shown) are sequentially formed over the resulting structure, and then patterned using a photoetching process, thereby forming bit lines
16
each having a polycide structure.
A second interlayer insulating layer
17
is formed over the resulting structure obtained after the formation of the bit lines
16
. A high temperature oxide (HTO) film
18
is subsequently deposited over the second interlayer insulating layer
17
. Using a photolithography process, a photoresist pattern
19
is then formed on the HTO film
18
in order to define buried contact hole regions. Thereafter, the HTO film
18
, second interlayer insulating layer
17
, and first interlayer insulating layer
13
are etched using the photoresist pattern
19
as a mask, thereby forming buried contact holes
20
through which the landing pads
12
formed on the respective source regions are exposed.
Referring to
FIG. 2
, removal of the photoresist pattern
19
is then carried out using an etching and stripping process. Thereafter, a nitride film is deposited over the resulting structure, and then etched back in accordance with a plasma dry etching process, thereby forming nitride spacers
22
on the side walls of the buried contact holes
20
. In this case, an over-etching is conducted to completely open the bottom surface of each buried contact hole
20
. During the etching process, the HTO film
18
is incidentally etched along with the nitride film at the top end of each buried contact hole
20
because of an insufficient etch selectivity between the nitride film and oxide film. As a result, the HTO film
18
has a slope or rounded corner at the top end of each buried contact hole
20
, as shown in FIG.
2
. Thus, each buried contact hole
20
has a flared opening at the top end thereof.
Referring to
FIG. 3
, a doped polysilicon layer
24
is then deposited over the resulting structure in such a manner that it completely fills the buried contact holes
20
a desired thickness.
Subsequently, a photoresist pattern
25
is formed on the polysilicon layer
24
using a photolithography process in order to define storage node regions, as shown in FIG.
4
. Using the photoresist pattern
25
as a mask, the polysilicon layer
24
is then etched in accordance with a plasma dry etching process, thereby forming storage node electrodes
24
a
being connected to the landing pads
12
on the source regions via the buried contact holes
20
.
The photoresist film pattern, which is to be used in the photoetching process for patterning the polysilicon layer for storage node electrodes, may often be misaligned from the buried contact holes. In such a case, however, the above mentioned conventional method involves problems because each buried contact hole has an inclined? top portion. That is, when the etching process is conducted at the inclined top portion of each buried contact hole, etching ions may scatter at that portion due to the above mentioned misalignment, thereby deflecting the etching direction. As a result, each storage node electrode may have a shape in which the polysilicon layer is partially recessed at a region corresponding to the top portion of the associated buried contact hole, as indicated by the reference numeral
26
in FIG.
4
. This results in a reduction in the cross-sectional area of the storage polysilicon layer at the top end of each buried
Ban Hyo-Dong
Park Young-Hun
Marger & Johnson & McCollom, P.C.
Owens Douglas W.
Samsung Electronics Co,. Ltd.
Thomas Tom
LandOfFree
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