Buried-channel MOS transistor and process of producing same

Details Buried-channel MOS transistor and process of producing same Buried-channel MOS transistor and process of producing same

1997-07-16

1999-08-03

Booth, Richard A.

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438305, 438527, 438919, H01L 21336

Patent

active

059337370

ABSTRACT:
In fabricating a buried p-channel MOS transistor using an n-type substrate, a shallow n-type diffused layer is formed by ion implantation in each of intended source and drain regions so as to become oppositely adjacent to the shallow p-type diffused layer under the gate electrode. After that p-type diffused layers to serve as source and drain are formed by ion implantation through the n-type diffused layers, and the implanted impurities are activated. In consequence, impurity concentration at the substrate surface becomes lower in the section right under each end of the gate electrode than in the gate middle sections. This measure brings about suppression of the short channel effect inherent to conventional buried-channel MOS transistors and makes it possible to shorten the physical gate length.

REFERENCES:
patent: 5329138 (1994-07-01), Mitani et al.
patent: 5486480 (1996-01-01), Chen
patent: 5527721 (1996-06-01), Farb
patent: 5580799 (1996-12-01), Funaki
patent: 5683923 (1997-11-01), Shimizu et al.
A. E. Schmitz et al., "High Performance Subhalf-Micrometer P-Channel Irnasistors for CMOS VLSI|" IEDM Technical Digest, (1984), pp. 423-426.
C. Mazure et al., "Design Considerations for Sub-0.35.mu.m Buried Channel P-MOSFET Devices", IEEE VLSO Symposium, Digest of Technical Papers, (1992), pp. 92-93.

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