Bump-on-lead flip chip interconnection

Details Bump-on-lead flip chip interconnection Bump-on-lead flip chip interconnection

2011-07-05

2011-07-05

Lee, Hsien-ming (Department: 2823)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

C257S737000, C257S778000, C257SE23021, C438S107000, C438S108000, C438S612000, C438S613000

Reexamination Certificate

active

07973406

ABSTRACT:
A semiconductor device has a semiconductor die with a plurality of bumps formed over the die. A substrate has a plurality of conductive traces formed on the substrate. Each trace has an interconnect site for mating to the bumps. The interconnect sites have parallel edges along a length of the conductive traces under the bumps from a plan view for increasing escape routing density. The bumps have a noncollapsible portion for attaching to a contact pad on the die and fusible portion for attaching to the interconnect site. The fusible portion melts at a temperature which avoids damage to the substrate during reflow. The noncollapsible portion includes lead solder, and fusible portion includes eutectic solder. The interconnect sites have a width which is less than 1.2 times a width of the conductive trace. Alternatively, the interconnect sites have a width which is less than one-half a diameter of the bump.

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