Built-in stress pattern on IC dies and method of forming

Details Built-in stress pattern on IC dies and method of forming Built-in stress pattern on IC dies and method of forming

1999-07-08

2001-04-17

Meier, Stephen D. (Department: 2822)

Active solid-state devices (e.g., transistors, solid-state diode

Lead frame

Small lead frame for connecting a large lead frame to a...

C257S676000, C257S203000

Reexamination Certificate

active

06218726

ABSTRACT:

FIELD OF THE INVENTION
The present invention generally relates to an IC die formed with a built-in stress test pattern and a method for forming such pattern and more particularly, relates to built-in stress test patterns on IC dies that can be formed at corners of each die by a double metal method of utilizing metal
1
and metal
2
layers with an isolation layer therein between and then encapsulating in a molding compound prior to subjecting the dies to a thermal cycling test and a method for forming such stress test patterns.
BACKGROUND OF THE INVENTION
In the fabrication of IC devices, a frequently seen mode of failure results form stress and strain in the bulk material used in forming the device. The stress and strain in the bulk material may be caused by the internal forces due to dislocations, excess vacancies and impurities in the material, growth around trapped foreign material, thermal gradients during processing, and changes in temperature after dissimilar materials are bonded together. For instance, vapor-deposited material of either an amorphous type, a polycrystalline type or a single-crystal type develops large internal stresses during the deposition process.
The stress and strain problem frequently occurs in the thin films formed of dissimilar materials on top of a silicon wafer. These dissimilar materials may be silicon, silicon oxide, metal conducting layers, passivation dielectric layers and polymeric based molding materials used in the encapsulation process. The structural built-up of wafers normally involves semiconductor-dielectricmetal sandwiching layers that are particularly susceptible to differential expansion-induced stress because of the large disparity between the thermal expansion coefficients of the various materials. In addition, the various films of different materials may have internal stresses built-in during the deposition process which may further increase the thermally-induced stress.
To determine the magnitude and the detrimental effect of the differential expansion-induced stress in an IC device, therefore, becomes an important task in the quality control or reliability determination of device fabricated. The type of reliability problems that are frequently seen in molded plastic packages of IC devices frequently involves cracking in the layers of thin films deposited on the silicon surface. A hot/cold thermal cycle test is one method used in reliability testing for determination of the differential expansion-induced stress, also known as thermo-mechanical stress resulting from disparity of expansion coefficience of the material layers which causes large relative displacements at the various material interfaces.
In an IC device that is formed with dies of substantially square dimensions, it has been noticed that the differential expansion-induced stress occurs most severely at the corner regions of the dies. The stress exists mostly in a form of shear stress between the material layers. The shear stress may severely affect the isolation between dielectric layer and metal layers and furthermore, the adhesion between a silicon oxide layer and a silicon surface thus presenting various reliability problems. Since most of the materials used in forming the metal layers, the dielectric layers and the isolation layers are fixed and cannot be changed, the selection of a plastic molding compound for encapsulating the IC package becomes an important factor. The selection of the molding compound must be carefully conducted such that the differential expansion-induced stress caused by a disparity of expansion coefficient between the molding compound and the various material layers must be minimized. It is therefore desirable to have an IC test die that can be formed with built-in stress test patterns for evaluating the undesirable effect of the different expansion coefficient between the materials.
It is therefore an object of the present invention to provide an IC die that is formed with built-in stress test pattern that does not have the drawbacks or shortcomings of the conventional test methods for molded-in stresses on IC packages.
It is another object of the present invention to provide an IC die that is formed with built-in stress test pattern that can be easily fabricated during the IC die fabrication process.
It is a further object of the present invention to provide an IC die that is formed with built-in stress test pattern without requiring additional fabrication steps than those normally required for forming the die.
It is another further object of the present invention to provide an IC die that is formed with built-in stress test pattern at corner regions of the die.
It is still another object of the present invention to provide an IC die that is formed with built-in stress test pattern that includes at least two stress patterns each formed at one of the four corner regions.
It is yet another object of the present invention to provide an IC die that is formed with at least two stress test patterns wherein each of the patterns is formed with a dielectric layer on the silicon substrate, a first metal layer, an electrically insulating material layer, and a second metal layer on top while the die is encapsulated in a molding compound.
It is still another further object of the present invention to provide a method for testing thermo-mechanical stresses in a plastic package of an IC die by first providing an IC die with built-in test patterns formed at least two of the comer regions, encapsulating the die in a molding compound, thermal cycling the package through a plurality of thermal cycles, and probing between the first and second plurality of metal traces in the test pattern to determine leakage currents and thermo-mechanical stresses.
It is yet another further object of the present invention to provide a method for testing thermo-mechanical stresses in a plastic package of an IC die by first forming built-in stress test patterns at a comer region which consists of a first metal layer formed in linear metal traces and a second metal layer formed in L-shaped metal bars on top of the first metal layer with an electrically insulating layer therein between.
SUMMARY OF THE INVENTION
In accordance with the present invention, an IC die that is formed with built-in stress test pattern and a method for performing thermo-mechanical stress testing on a plastic package of an IC die are provided.
In a preferred embodiment, an IC die formed with built-in stress test pattern is provided which includes a silicon substrate that has four corner regions, and at least two stress test patterns each formed at one of the four corner regions, the at least two stress test patterns each includes a dielectric material layer on the silicon substrate, a first plurality of diagonally positioned linear metal traces formed of a first metal, an electrically insulating material layer on top of the first plurality of diagonally positioned metal traces, and a second plurality of L-shaped metal bars formed of a second metal positioned with the two sides of L parallel to the two sides of a corner region and overlapping the first plurality of metal traces with the electrically insulating material layer therein between.
In the IC die formed with built-in stress test pattern, each of the second plurality of L-shaped metal bars being electrically connected to a contact pad adapted for contact probing. The at least two stress test patterns may include three stress test patterns formed at three of the four corner regions. The IC die may further include alignment marks formed at a fourth corner region, the IC die may be one of a multiplicity of dies formed on a silicon wafer. The second plurality of L-shaped metal bars may include between about two and about ten metal bars.
In the IC die formed with built-in stress test pattern, the second plurality of L-shaped metal bars may include preferably between about three and about five metal bars. The second plurality of L-shaped metal bars may be arranged parallel to each other. The second plurality of L-shaped metal bars overlaps the firs

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