Built-in self-testing for embedded memory

Details Built-in self-testing for embedded memory Built-in self-testing for embedded memory

2000-05-08

2003-12-23

Tu, Christine T. (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S730000

Reexamination Certificate

active

06668347

ABSTRACT:

BACKGROUND
This invention relates to a built-in self-test unit (BIST) for embedded memory.
Application specific integrated circuits (ASICs) are widely used in various electronic components and often include complete memory systems. Generally, there are two methods for testing embedded memory within an integrated circuit. One method uses external test equipment connected to external pins of the chip and tests the embedded memory by generating various test patterns. If the data read from the memory system does not match the data written, the memory system is deemed defective. The use of the external test equipment requires that each embedded memory module be connected to one or more externally accessible pins, thereby increasing routing overhead and pin count.
A second method is to incorporate a built-in self-test unit (BIST) within the integrated circuit in order to test the embedded memory. The BIST is activated when the integrated circuit receives power, or when triggered from an external signal, and tests the embedded memory by applying a test pattern and comparing the applied test pattern to data read from the embedded memory. Based on the comparison, the BIST sets an externally available pin to indicate whether or not an error was detected. This approach reduces the number of external connections needed for such testing and allows multiple memory modules to be tested simultaneously, thereby reducing test time.


REFERENCES:
patent: 5349587 (1994-09-01), Nadeau-Dostie et al.
patent: 5469443 (1995-11-01), Saxena
patent: 5675545 (1997-10-01), Madhavan et al.
patent: 6452848 (2002-09-01), Obremski et al.

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