Built-in self-testing for double data rate input/output

Details Built-in self-testing for double data rate input/output Built-in self-testing for double data rate input/output

2001-11-27

2004-11-09

Ton, David (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C713S152000

Reexamination Certificate

active

06816991

ABSTRACT:

BACKGROUND
This invention relates to the field of computer systems. More particularly, a system and methods are provided for facilitating built-in self-testing of a double data rate circuit.
Integrated circuits are generally subjected to rigorous testing (e.g., structural, manufacturing, operational) in order to ensure their correct operation. Conventional testing equipment has usually been adequate to test input/output circuits and interfaces at their designed operating speeds.
However, the operational data rates of newer input/output circuits and interfaces are increasing ever higher. In particular, communication rates have significantly increased with the advent of double data rate (DDR) techniques. As a result, conventional testing equipment and techniques are now inadequate for testing circuits and interfaces that use DDR, particularly at their designed or intended operating rates. Thus, while traditional input/output circuits could be connected to external equipment to test their interfaces, DDR circuits operate too fast for traditional equipment, thereby necessitating specialized and expensive testing equipment. As the number of integrated circuits that employ DDR increase, this problem will become ever more apparent.
In addition, requiring external equipment for testing input/output circuits limits the flexibility of such testing. For example, once an integrated circuit that is configured for testing with external equipment is installed in a device, regular testing of the circuit becomes infeasible.
SUMMARY
Thus, in one embodiment of the invention, an apparatus and method are provided for self-testing a DDR input/output (I/O) circuit or interface at its operating speed. Illustratively, the apparatus may comprise a macro cell with built-in self-test (BIST) logic. A multi-line I/O interface for an integrated circuit (IC) may be constructed using a plurality of these cells, with the whole interface being self-testable. Greater flexibility is afforded the interface design than would be possible if the interface required external equipment for testing.
In another embodiment of the invention, one type of macro cell may be implemented for self-testing the input logic or circuitry of a DDR interface, another type for self-testing the output. Yet another type of macro cell may be implemented for self-testing a clock used for the DDR input and/or output.
A BIST controller is also provided for an I/O interface (e.g., of an application specific integrated circuit) built using the macro cells of an embodiment of the invention. In this embodiment, a relatively slow JTAG controller (according to IEEE 1149.1) may initiate self-testing through the BIST controller, which would operate at the I/O speed of the interface. Illustratively, the IEEE 1149.1 tap collects the final BIST results.


REFERENCES:
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patent: 6545927 (2003-04-01), Muller
patent: 6574758 (2003-06-01), Eccles
patent: 6662136 (2003-12-01), Lamb et al.
patent: 6691272 (2004-02-01), Azim

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