Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2001-03-13
2004-07-27
Tu, Christine T. (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S743000, C714S730000, C711S200000
Reexamination Certificate
active
06769084
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor testing device and a method for testing semiconductor memories; in particular a device and method having a built-in self-tester and a linear feedback shift register for testing semiconductor memories.
2. Discussion of Related Art
BIST (built-in self test) is a technique for testing embedded memory using a circuit having a test algorithm. A conventional BIST circuit is shown in FIG.
1
. As shown, the BIST circuit
100
includes an address generator
120
for generating addresses to access the locations of Memory
150
. The Data Generator
120
generates the data to be tested, and a comparator
140
compares data read from Memory
150
against the data written into the memory. BIST controller
110
typically includes a stored program which when executed, applies the proper control signals to the address generator
120
, data generator
130
, and comparator
140
to test the memory
150
. BIST controller
110
also receives the compared data from comparator
140
and determines whether the test has passed or failed.
A March test algorithm is commonly employed as the test algorithm stored in the BIST controller for testing the embedded memory. The March test algorithm implements a test sequence which tests each bit of each location in the memory by causing both a ‘0’ and a ‘1’ value to be written to and read from the memory. The address to the memory are incremented and decremented in sequential order until all locations are tested. The March test sequence is:
(W
D
)↑(R
D
, W
D′
)↑(R
D′
, W
D
)↓(R
D
, W
D′
)↓(R
D′
, W
D
)
(R
D
)
Wherein the symbols ↑, ↓, and
denote directions of counting addresses of: “up” (address increment) “down” (address decrement), and “up or down” (increment or decrement), respectively. The symbols W and R represent writing and reading, respectively. D is a data value, either a ‘O ’ or ‘1’ and D′ denotes the opposite of D. W
D
means a writing operation with data D and R
D′
means a reading operation with D′. The parenthesis “( )” denotes the operations which are carried out for all the addresses and if more than one operation is within the parenthesis, both operations are carried out at the same address location. For example, “(R
D
, W
D′
)” means D is read out of and D′ is written into the same location before the address is changed. The March test method detects stuck-at faults at each cell, but cannot detect coupling and address faults. See “An Effective BIST Scheme for Ring-Address Type FIFOs.” By Y. Zodan, A. J. Van De Goor, and Ivo Schanstra, IEEE Int. Test Conference, Washington D.C., pp. 378-387, Oct. 1994.
U.S. Pat. No. 5,706,293 to Kim et al. describes a test method which detects address faults and coupling faults in addition to the stuck-at faults detected by the March test algorithm. The addressing described in the ‘293 Patent is unidirectional (single-order address). The ‘293 patent describes use of ‘Address Data Backgrounds’ as test data which tests all memory locations for the above-described faults. The Address Data Backgrounds (ADBs) are pseudo-random data which can be generated by a linear feedback shift register (LFSR). The ‘293 patent discloses a test pattern of:
(W
D
), (R
D
, W
D′
), (R
D′
, W
D
), (R
D
).
ADB is defined in the ‘293 patent as a union of all the data that two (2) random cells having mutually different addresses can have. In the ‘293 test method, an ADB from a group is selected as an initial data written into all the locations of the memory. Upon reading the ADBs first written into all the locations, the inverse or opposite value of the same ADB is written into all the locations of the memory. Addressing of the memory is by sequential incrementation. The inverted ADB data is read and when the inverted data is correctly read, data from the same ADB group is written to and read from each location of the memory again. These steps are repeated for each of the Address Data Backgrounds. In the ‘293 test method, counters such as carry propagation adder, carry safe adder, or ripple counter can be used to provide a unidirectional count from zero to the most significant location of the memory. The ‘293 patent is commonly assigned to the applicant and the disclosure of U.S. Pat. No. 5,706,293 is incorporated by reference herein.
Referring again to
FIG. 1
, the address generator
120
in BISTs typically is a counter which is capable of repeatedly counting up or counting down sequentially. A sequential up-down counter is used to implement the March test algorithm. An up-down counter sequentially counts up or down by adding or subtracting one to or from the previous count. Propagation half adders are commonly used to add or subtract to the count. This requires propagating a carry from the least significant bit (LSB) to the most significant (MSB) of an address string. The time of propagation of the carry from the LSB to the MSB of all the address bits represent the cycle time which must be allocated for each test cycle of the BIST tester. Thus, the larger the memory capacity, the wider the address, and the cycle time needed for the address generator/counter must necessarily increase.
A problem is encountered when a BIST circuit is used to test a high capacity memory at operational speed, i.e., at the operating speed of the CPU. Recently, CPUs that operate at 1.5 Ghz are widely available. In order to test a high capacity memory at operational speed, the conventional up-down counter cannot be employed because the carry cannot propagate through the entire counter within the cycle time of a CPU cycle at operational speed.
Further, a BIST circuit is typically embedded within the memory on the same chip. To test a higher capacity memory, the address is wider or has more bits and more adders are needed in the up-down counter. This results in an increased size requirement for the BIST circuit, compromising valuable real estate of the semiconductor chip.
Accordingly, a need exists for a BIST circuit and method for testing semiconductor memories which avoid the above-discussed problems. The desired BIST circuit and method should be capable of generating addresses for testing all locations of the memory at normal CPU operational speed and the BIST circuit does not occupy a large chip area.
SUMMARY OF THE INVENTION
According to an aspect of the present invention, a semiconductor device is provided for testing a memory having N locations, the device comprising: a Linear Feedback Shift Register (LFSR) for creating unidirectional pseudo-random (log
2
N)-bit address patterns, the address patterns being used as addresses for memory locations to be tested; a data generator for generating data patterns based on the address patterns generated by the LFSR, said data patterns are grouped into (log
2
N)+1 Address Data Background (ADB) groups, each of the ADB groups having N locations, said data patterns for use as data input to the memory for testing; a comparator for comparing the data input to the memory against the data output from the memory for data integrity verification; and a built-in self test (BIST) controller, operatively connected to the LFSR, data generator, and comparator, for controlling testing of the memory.
Preferably, the data patterns include in each location data represented by a first logic level during a first test step and a second logic level during a second test step, wherein one of the ADB groups includes data represented by logic level low in the entire width of each location, the entire width being one or more bits.
According to a preferred embodiment of the invention, (log
2
N) groups of the (log
2
N)+1 ADB groups include at each location corresponding to an address generated by the LFSR, data having the same logic level as the logic level of address data in a predefined bit position of the address.
Preferably, each of the succeeding (log
2
N) ADB groups of the (log
2
N)+1 ADB groups is divided into a first subgrou
Kim Heon Cheol
Park Jin-Young
F.Chau & Associates LLC
Samsung Electronics Co,. Ltd.
Tu Christine T.
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