Built-in self test circuit and test method for storage device

Details Built-in self test circuit and test method for storage device Built-in self test circuit and test method for storage device

2007-04-17

2007-04-17

Ton, David (Department: 2138)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S719000, C714S723000

Reexamination Certificate

active

11089232

ABSTRACT:
A built-in self test circuit includes a capture register storing data transmitted from a memory device, an operation controller controlling operation of the memory device and the capture register, a hold controller executing a hold operation to stop a read operation and a write operation of the memory device by transmitting a hold signal to the operation controller, and a test control circuit controlling the operation controller to transmit a capture signal so that the capture register stores the data to the capture register.

REFERENCES:
patent: 6343366 (2002-01-01), Okitaka
patent: 6359818 (2002-03-01), Suzuki
patent: 6643807 (2003-11-01), Heaslip et al.
patent: 6728916 (2004-04-01), Chen et al.
patent: 6829728 (2004-12-01), Cheng et al.
patent: 7036064 (2006-04-01), Kebichi et al.
patent: 2004-022095 (2004-01-01), None

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