Built-in programmable self-diagnostic circuit for SRAM unit

Details Built-in programmable self-diagnostic circuit for SRAM unit Built-in programmable self-diagnostic circuit for SRAM unit

2001-07-09

2002-10-01

Elms, Richard (Department: 2824)

Static information storage and retrieval

Read/write circuit

Testing

C714S733000

Reexamination Certificate

active

06459638

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application Ser. no. 90107845, filed Apr. 2, 2001.
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a built-in testing circuit for a static random access memory (SRAM) unit. More particularly, the present invention relates to a built-in programmable self-diagnostic circuit for an SRAM unit capable of finding the location of faulty devices within the SRAM unit.
2. Description of Related Art
Due to the rapid progress in semiconductor manufacturing technologies, the quantity of devices on an integrated circuit (for example, a system-on-chip (SOC)) has increased exponentially, especially for static random access memory (SRAM). Before an SRAM unit is ready for shipment, devices inside the SRAM must be thoroughly tested. However, to test each one of the devices inside the SRAM requires vast numbers of testing leads. Hence, special methods and circuits that require fewer leads have been developed to test SRAM devices.
FIG. 1
is a block diagram showing a conventional built-in self-testing circuit for an SRAM unit. As shown in
FIG. 1
, a system-on-chip
10
having a built-in test circuit
12
and a static random access memory (SRAM) unit
14
is provided. The built-in test circuit
12
has a plurality of testing leads for receiving test instructions and test pattern signals and outputting test results. The built-in test circuit
12
generates test instructions (such as read or write instructions) and test pattern signals (such as address, input/output data or control signals) according to data in a built-in look-up table. The test instructions and test pattern signals are used to test the various functions of the SRAM unit
14
.
In general, testing functions of the built-in test circuit
12
are designed together with the system-on-chip (SOC)
10
. Therefore, the testing functions of the built-in test circuit
12
are fixed after fabrication of the SOC
10
is completed. Because the testing functions are already fixed, it is impossible to initiate the testing of other functions. In addition, even if faults are found in the SRAM unit
14
through testing, the built-in test circuit
12
has no means of pinpointing the exact location of the fault for subsequent repair.
FIG. 2
is a block diagram showing another conventional built-in self-testing circuit for a SRAM unit. As shown in
FIG. 2
, a system-on-chip
20
having a microprocessor
22
, a read-only-memory (ROM) unit
24
and a static random access memory (SRAM) unit
26
is provided. The microprocessor
22
has a plurality of test leads for receiving test instructions and test pattern signals and outputting test results.
After receiving test instructions and test patterns, the microprocessor
22
reads out test instructions (such as a read or a write instruction) and test signal patterns (such as address, input/output data or control signals) from the ROM unit
24
. Thereafter, various functions of the SRAM unit
26
are tested. However, a test circuit having both a microprocessor and a ROM unit will occupy a large wafer area. Since the test circuit is probably only used once for testing the SRAM unit and has no other functions thereafter, the production of such a test circuit wastes wafer area and increases production cost.
SUMMARY OF THE INVENTION
Accordingly, one object of the present invention is to provide a programmable built-in self-diagnostic circuit for testing a static random access memory (SRAM) unit. The circuit is able to pinpoint the exact location of a fault in the SRAM unit while occupying less wafer area and costing less to produce than conventional test circuits.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a programmable built-in self-diagnostic method for testing the integrity of a SRAM unit. First, a test mode or an analysis mode is selected. A test instruction is read according to the selected mode and then the test instruction is checked to determine if the instruction is a terminal read instruction. If the instruction is terminal, a test termination signal is issued. On the other hand, if instruction in non-terminal, the instructions demanded by a test instruction set are executed. Thereafter, the termination of the test instruction set is checked. If the work demanded by the test instruction set is finished, control is returned to the step of reading the next test instruction. On the other hand, if the work demanded by the test instruction set is unfinished, the results obtained from the test instruction set are checked to determine if errors are produced. If no faults are found as a result of executing the test instruction set, control is returned to the step of executing the test instruction set. Conversely, if faults are found in the results of executing the test instruction set, an error signal and an error operation code are produced so that the exact location of the fault in the SRAM unit can be found. Finally, control is returned to the execution of the test instruction set.
This invention also provides a programmable built-in self-diagnostic circuit for detecting any faults in a SRAM unit. The circuit includes a plurality of multiplexers, a demultiplexer, a test pattern generator, a fault location indicator and a controller. The multiplexers are coupled to the SRAM unit for providing a test pattern signal to the SRAM unit. The demultiplexer is coupled to the SRAM unit for receiving output data from the SRAM unit. The test pattern generator is coupled to the multiplexers and the demultiplexer. The test pattern generator receives a test instruction set for generating a test pattern signal and sending the signal to the multiplexers. The test pattern generator also determines if the execution of the test instruction set is finished or not so that a termination signal can be issued. The test pattern generator also receives output data from the demultiplexer and compares it with internally stored data. When the output data and internally stored data are non-identical, an error signal and an error operation code are issued. The fault site indicator is coupled to the test pattern generator. The fault location indicator issues a test abnormal signal on receiving an error signal. The error operation code is subsequently transmitted serially to find the exact fault location in the SRAM unit. The controller is coupled to the test pattern generator. The controller permits a selection between a test mode and an analysis mode. A test instruction is read according to the mode selected. The read-out test instruction generates a test instruction set according to a look-up table. The test instruction set is output to the test pattern generator. The controller also receives the termination signal and determines if the reading of instructions from the test instruction set is complete or not.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.


REFERENCES:
patent: 5301156 (1994-04-01), Talley
patent: 5577050 (1996-11-01), Bair et al.
patent: 6067262 (2000-05-01), Irrinki et al.
patent: 6137734 (2000-10-01), Schoner et al.

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