Breakdown drain extended NMOS

Details Breakdown drain extended NMOS Breakdown drain extended NMOS

2000-05-17

2003-05-06

Whitehead, Jr., Carl (Department: 2813)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S286000, C438S545000, C438S585000

Reexamination Certificate

active

06559019

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a drain extended NMOS semiconductor device which has increased breakdown voltage and requires fewer processing steps for fabrication than do prior art NMOS devices with equivalent breakdown voltages.
2. Brief Description of the Prior Art
In the fabrication of NMOS devices, especially for automotive applications, breakdown voltages of such devices required to be at least 40 volts. The prior art standard process for fabrication of NMOS devices yields breakdown voltages of about 33 volts. Additional processing steps must be added to the standard NMOS fabrication process in order to obtain a breakdown voltage of at least 40 volts.
A standard prior art process for fabrication of NMOS transistors generally involved providing a semiconductor material having an lightly doped p-type well therein. The material was then masked to provide an opening in the central region through which there was provided a tank having a shallow light n-type implant. The device was then masked and a heavy doping n-type was implanted at the surface into the central portion of the previously masked region to form a drain region and in the p-type well spaced from the previously masked region to provide a source region. A further masking and heavy doping p-type then takes place in the p-type well remote from the drain to form a backgate. At some time during the process, a heavy doping p-type is provided in the tank between the source and drain regions to provide a channel stop in standard manner. A gate oxide is then formed over the device surface between the source and drain regions and a polysilicon gate electrode is then formed over the gate oxide, both in standard manner.
SUMMARY OF THE INVENTION
In accordance with the present invention, the above described prior art NMOS device is altered by removing the channel stop and by providing a deep tank having a lightly doped n-type region over which is a resulting deep lightly region doped with both n-type and p-type with an excess of n-type. The NMOS device in accordance with the present invention has been initially tested and found to have a breakdown voltage of 131 volts, this being far in excess of the breakdown voltage presently required in the automotive industry.
Briefly, there is provided a semiconductor device having a lightly doped p-type well with a central region of the well having a tank which was formed by masking the well and implanting a deep n-type implant and a more shallow implant of both n-type and p-type which has a slight excess of n-type dopant to provide a centrally located tank having a lightly doped n-type region over a lightly doped n-type region with the surface being very lightly doped n-type and being a graded structure in the direction of the device surface and p-type region of the well. A highly doped n-type drain region is disposed within the lightly doped n-type region and a heavily doped n-type source region is disposed within the p-type well spaced from the central region. A highly doped p-type backgate is disposed in the lightly doped p-type well spaced from the source region remote from the central region. A gate oxide is disposed on the surface of the device between the source and drain regions with a polysilicon gate electrode disposed thereover.
As noted above, no channel stop is used, there being merely the lightly doped P-type region of the tank and the lightly doped n-type central region in the channel to provide essentially a graded junction and, thereby, a low intensity field at the junction. The breakdown voltage of the above described NMOS transistor was measured at 131 volts which is far in excess of the breakdown voltages achievable in the prior art.
The above described NMOS transistor is fabricated by providing a semiconductor material having a lightly doped p-type well therein. The material is then masked to provide an opening in the central region through which there is provided a tank having a light doping n-type implant which will be driven to the desired depth by temperature and a shallow light doping n-type and a light doping p-type, there being a slight excess on n-type. With the subsequent diffusion of the implanted dopant, the surface of the device within the masked region will be very lightly doped n-type. The device is then masked and a heavy dopant n-type is implanted at the surface into the central portion of the previously masked region to form a drain region and in the p-type well spaced from the previously masked region to provide a source region. A further masking and heavy implant p-type then takes place in the p-type well remote from the drain to form a backgate. A gate oxide is then formed over the device surface between the source and drain regions and a polysilicon gate electrode is then formed over the gate oxide, both in standard manner.


REFERENCES:
patent: 5866460 (1999-02-01), Akram et al.
patent: 5869866 (1999-02-01), Fulford, Jr. et al.
patent: 6107129 (2000-08-01), Gardner et al.

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