Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2007-05-15
2007-05-15
Decady, Albert (Department: 2138)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S726000
Reexamination Certificate
active
10701479
ABSTRACT:
A circuit and a method are provided for testing the enable function of Boundary Scan Register bits that control the driver of unconnected I/O pins of an 1149.1-compliant IC during the IC's reduced pin-count access manufacturing test, and to test the connections to these pins during the test of a circuit board containing the IC, without causing excessive current if a pin is inadvertently short circuited.
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IEEE Standard Test Access Port and Boundary-Scan Architecture; IEEE Std1149.1-1990.
Gauthier Pierre
Nadeau-Dostie Benoit
Sunter Stephen K.
De'cady Albert
LogicVision, Inc.
Nguyen Steve
Prouix Eugene E.
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