Boundary scan system with address dependent instructions

Details Boundary scan system with address dependent instructions Boundary scan system with address dependent instructions

1997-11-07

2000-02-29

Moise, Emmanuel L.

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

714730, G01R 3128

Patent

active

060322799

ABSTRACT:
Boundary Scan integrated circuits are provided with a plurality of new registers between two dedicated pins, Test Data In (TDI) and Test Data Out (TDO) pins. The new registers include an address register and a plurality of test data registers which are addressable by the address register using address-dependent instructions in the instruction register (IR). Instructions for the addressable registers may be steered to the correct register with an ADDLOAD instruction placed in the instruction register followed by an address-dependent instruction. The ADDLOAD instruction makes the address register active between the TDI and TDO pins. Any instruction from a set of address-dependent instructions may be steered to any register handling address-dependent instructions allowing a small number of instructions to be used in a large number of addressable data registers. At the same time non-addressable registers, such as the Boundary Scan register, use address-independent instructions.

REFERENCES:
patent: 5155732 (1992-10-01), Jarawala et al.
patent: 5355369 (1994-10-01), Greenbergerl et al.
patent: 5394403 (1995-02-01), Klein
patent: 5459737 (1995-10-01), Andrews
patent: 5477545 (1995-12-01), Huang
patent: 5898704 (1999-04-01), Kawano

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