Borderless contact etch process with sidewall spacer and selecti

Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material

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Details

438639, 438695, H01L 214763

Patent

active

059603186

ABSTRACT:
A method of fabricating a self-aligned borderless contact in a semiconductor device. The semiconductor device includes a first conductor level, a patterned conductor level defining a pair of spaced apart conducting segments, and a dielectric insulating layer disposed between the first conductor level and the patterned conductor level, and over the pair of spaced apart conducting segments of the patterned conductor level. The method comprises the steps of etching a contact hole in a selected region of the dielectric insulating layer which lies above and is substantially aligned between the pair of the segments. The etching continues through the dielectric insulating layer so that a portion of the dielectric insulating layer remains between the contact hole and the first conductor level. A spacer is formed which lines the contact hole. The remaining portion of the insulating layer which extends between the contact hole and the first conductor level is then etched to extend the contact hole to the first conductor level. The spacer substantially prevents the erosion of the pair of spaced apart segments during the etching of the remaining portion of the insulating layer. The contact hole is then filled with a conductive material to form the self-aligned borderless contact. The borderless contact formed by the present method is electrically isolated from the pair of spaced apart conducting segments of the patterned conductor level by the dielectric insulating layer.

REFERENCES:
patent: 4182636 (1980-01-01), Dennard et al.
patent: 4409722 (1983-10-01), Dockerty et al.
patent: 5112763 (1992-05-01), Taylor et al.
patent: 5118382 (1992-06-01), Cronin et al.
patent: 5118634 (1992-06-01), Neudeck et al.
patent: 5157000 (1992-10-01), Elkind et al.
patent: 5216281 (1993-06-01), Butler
patent: 5217919 (1993-06-01), Gaul et al.
patent: 5225040 (1993-07-01), Rohner
patent: 5250829 (1993-10-01), Bronner et al.
patent: 5286344 (1994-02-01), Blalock et al.
patent: 5384281 (1995-01-01), Kenney et al.
patent: 5420057 (1995-05-01), Bennett et al.
patent: 5476806 (1995-12-01), Roh et al.
patent: 5478768 (1995-12-01), Iwasa
patent: 5583368 (1996-12-01), Kenney
patent: 5605862 (1997-02-01), Givens et al.
patent: 5651857 (1997-07-01), Cronin et al.
patent: 5677231 (1997-10-01), Maniar et al.
patent: 5792703 (1998-08-01), Bronner et al.

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