Boosted sensing ground circuit

Details Boosted sensing ground circuit Boosted sensing ground circuit

1998-12-29

2001-03-06

Dinh, Son T. (Department: 2824)

Static information storage and retrieval

Read/write circuit

Precharge

C365S203000, C365S207000

Reexamination Certificate

active

06198677

ABSTRACT:

FIELD OF THE INVENTION
It was proposed in IEEE Journal of Solid State Circuits, Vol. 30, No.4, April, 1995, p.471 a concept of boosting the ground level of the sense amplifier. The purpose of the Boosted Sense Ground (BSG) implementation is to reduce the current leakage of the unsolicited cells. One major disadvantage is that the boosted ground voltage is very unstable and tends to be disturbed during sensing as well as data transferring. The BSG voltage level is generally about 0.3 to 0.6 volts which is generated by an internal charge pump and distributed among the arrays. As to those skilled in the art should know such a low voltage level is inherently harder to generate than those of higher voltage levels. Also due to the limited design area for the charge pump, a strong pump is usually not available. Under this circumstance, to maintain the BSG level would be very difficult. To solve this problem, the above-identified article proposed a column decoded sensing scheme, where a complicated sense amplifier was designed with large number of devices. This develops a much larger array size.
Thus the need exists for an improved DRAM array sensing techniques for low voltage operation using a boosted sense ground scheme that is more stable. The solution should be at least as or more effective and the circuit size more compact than existing circuits. The present invention addresses these needs.
SUMMARY OF THE INVENTION
An object of this invention is to provide as improved memory array sensing technique for low voltage operation using a boosted sense ground scheme that is more stable.
Another object of the present invention is to provide an improved DRAM array sensing technique for low voltage operation with a boosted sense ground scheme that is more effective and the circuit size more compact than existing circuits.
These and other objectives are obtained with a new noise control circuit which connects the boosted sense ground node to ground in two specific period of times so that the BSG bouncing is minimized. Preferably these two periods are at the beginning of setting the n-type latch and when the data is transferring and column switch. A pulse of n-latch set signal and together with a control signal are used to activate the noise control circuit. The noise control circuit can also include a n-FET diode with its gate connected to the source and its drain tied to the Bt-line equalization power supply. It is more preferable to use a low threshold voltage of n-FET device with Vt at 0.55 volts to form the clamp diode.


REFERENCES:
patent: 5257232 (1993-10-01), Dhong et al.
patent: 5508965 (1996-04-01), Nomura et al.
patent: 5619465 (1997-04-01), Nomura et al.
patent: 5646900 (1997-07-01), Tsukude et al.
patent: 5949729 (1999-09-01), Suyama et al.
Tsukasa Ooishi, et al., “An Automatic Temperature Compensation of Internal Sense Ground for Subquarter Micron DRAM's,” IEEE Journal of Solid-State Circuits, vol. 30, No. 4 (Apr. 1995).
Takahiro Tsuruda, et al. “High-Speed/High-Bandwidth Design Methodologies for On-Chip DRAM Core Multimedia System LSI's,” IEEE Journal of Solid-State Circuits, vol. 32, No. 3 (Mar. 1997).

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