Bonding of silicon wafers

Details Bonding of silicon wafers Bonding of silicon wafers

1999-05-28

2001-05-01

Whitehead, Jr., Carl (Department: 2822)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S974000, C257S777000

Reexamination Certificate

active

06225154

ABSTRACT:

The invention concerns fabrication of a structure called SOI, Silicon On Insulator. The SOI structure can be viewed as three-layered: the Silicon layer (the “S” in SOI) is attached to the Insulator (the “I” in SOI), using a layer of spin-on glass (SOG) as an adhesive.
BACKGROUND OF THE INVENTION
Very Large Scale Integration (VLSI), Ultra Large Scale Integration (ULSI), and higher-density approaches to integrated circuit fabrication require reduced parasitic capacitances. One approach to reducing these capacitances is the use of silicon-on-insulator (SOI) techniques.
In SOI fabrication, layers of device-quality silicon are formed upon insulating islands, as shown in FIG.
1
. In one method of SOI fabrication, silicon is grown upon sapphire (the INSULATOR in
FIG. 1
) in an epitaxial growth step.
In another method, shown in
FIGS. 2A-2D
, oxygen (or nitrogen) is implanted through silicon, to form a buried layer of silicon dioxide (or silicon nitride). After implantation, an epitaxial layer
3
may be added to the silicon located above the implant, in order to provide a thicker silicon layer. The silicon layer
6
provides the device-quality silicon.
SOI technology is not without drawbacks. Epitaxial approaches have several disadvantages.
1. Epitaxial growth is expensive.
2. The epitaxially grown silicon is not always sufficiently defect-free.
3. Adhesion problems can result between the epitaxial layer and the substrate.
4. Stresses can occur at the silicon-insulator interface, because of (a) different thermal coefficients of expansion, and (b) mismatch between the inter-atomic spacing of the silicon, compared with that of the insulator.
Implantation approaches also face disadvantages.
1. The implantation approach requires implantation equipment, which is expensive.
2. During implantation, the implanted species disrupts the crystalline structure of the silicon. An annealing step is required to restore proper crystallinity of the silicon.
3. Practical implantation energies cannot supply the required implant depth for most implant species. Further, a layer
3
in
FIG. 2C
is frequently obtained, in which no substantial implantation occurred. Sometimes, this layer
3
may be too thin, requiring that the thickness of layer
3
be increased. The increase in thickness is generally accomplished by epitaxial techniques, which require added processing steps, shown in FIG.
2
D.
4. There is a limit to the amount of implanted species which can be implanted. Thus, the doping concentration, and thus the conductivity, of the implanted layer
6
in
FIG. 2D
is limited.
OBJECTS OF THE INVENTION
It is an object of the invention to provide an improved silicon-on-insulator structure.
It is a further object of the invention to provide a method of fabricating two single-crystal layers of silicon which are bonded together.
It is a further object of the invention to provide a method of fabricating two single-crystal layers of silicon which are bonded together, and can withstand the high temperatures used in subsequent fabrication steps.
SUMMARY OF THE INVENTION
In one form of the invention, two silicon wafers are bonded together using spin-on-glass (SOG). Then, one of the layers is polished to reduce its thickness. Integrated circuits are fabricated on the thinner, polished, layer.


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