Bond pad scheme for Cu process

Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Bump leads

Reexamination Certificate

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C257S738000, C257S779000

Reexamination Certificate

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06844626

ABSTRACT:
A novel method of forming a bond pad of a semiconductor device and a novel bond pad structure. Two passivation layers are used to form bond pads of a semiconductor device. A portion of the second passivation layer resides between adjacent bond pads, preventing shorting of the bond pads during subsequent wire bonding processes or flip-chip packaging processes.

REFERENCES:
patent: 6187680 (2001-02-01), Costrini et al.
patent: 6709965 (2004-03-01), Chen et al.
Wolf, Stanley, et al., “Silicon Processing for the VLSI Era, vol. 1: Process Technology,” 2ndEdition, 2000, pp. 841-854, Lattice Press, Sunset Beach, CA.

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