Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Patent
1996-05-02
1997-12-30
Tsai, Jey
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
438253, 438257, 438258, 438199, H01L 218242
Patent
active
057029881
ABSTRACT:
A method of forming semiconductor logic devices and memory devices on a single semiconductor substrate is described. Memory devices that may be formed include nonvolatile memory, DRAM and/or SRAM (poly-load or TFT). A semiconductor substrate having a first conductivity type dopant is provided. A triple-well structure is formed in the semiconductor substrate, having N-well regions, P-well regions, and P-well in N-well regions. Field isolation regions are formed. A cell is formed for each memory device in the memory regions. A channel implant is performed in the substrate for each of the logic and memory devices. A primary gate and gate oxide is formed for each of the logic and memory devices. LDD (Lightly Doped Drain) active regions and heavily doped source/drain regions are formed adjacent to each gate. Additional memory structures are formed, such as a DRAM capacitor. An interlevel dielectric and contact openings therein are formed. One or more metal layers are subsequently deposited over the inter-level dielectric layer and in the openings to make contact to the contact regions.
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Ackerman Stephen B.
Saile George O.
Taiwan Semiconductor Manufacturing Company , Ltd.
Tsai Jey
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