Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2007-02-13
2007-02-13
Dang, Trung (Department: 2823)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C257SE21682, C257SE21690
Reexamination Certificate
active
10513163
ABSTRACT:
The invention relates to a bit line structure having a surface bit line (DLx) and a buried bit line (SLx), the buried bit line (SLx) being formed in a trench with a trench insulation layer (6) and being connected to doping regions (10) with which contact is to be made via a covering connecting layer (12) and a self-aligning terminal layer (13) in an upper partial region of the trench.
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patent: 5796167 (1998-08-01), Koga
patent: 6008522 (1999-12-01), Hong et al.
patent: 6348374 (2002-02-01), Athavale et al.
patent: 6734482 (2004-05-01), Tran et al.
patent: 6787843 (2004-09-01), Tempel
patent: 2003/0007386 (2003-01-01), Georgakos et al.
patent: 10062245 (2000-12-01), None
patent: WO 01/99152 (2001-12-01), None
PCT International Search Report PCT/DE 03/02676 , Mar. 17, 2004.
Kakoschke Ronald
Shum Danny
Tempel Georg
Brinks Hofer Gilson & Lione
Dang Trung
Infineon - Technologies AG
Katz James L.
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