Bitline precharge circuit of multi-sectional memory array

Details Bitline precharge circuit of multi-sectional memory array Bitline precharge circuit of multi-sectional memory array

1989-05-05

1991-04-09

Hecker, Stuart N.

Static information storage and retrieval

Read/write circuit

Precharge

36523003, G11C 700, G11C 800

Patent

active

050070231

ABSTRACT:
The invention relates to a bit line precharge circuit of a multi-sectional memory array in which a first set of circuits gate a section decoding signal and a main bit line precharge pulse and a second set of circuits gate the section decoding signal and a main data line precharge pulse. The resultant signals from the first and second sets of circuits are fed into respective inverter circuits and then respectively into a bit line precharge circuit and a data line precharge circuit so that the operation margin of the section decoding signal increases by as much as the width of the main bit line precharge pulse.

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patent: 4858189 (1989-08-01), Ogiue et al.
patent: 4928268 (1990-05-01), Nogle et al.
patent: 4935901 (1990-06-01), Sasaki et al.

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