Bit line precharge in embedded memory

Static information storage and retrieval – Read/write circuit – Precharge

Reexamination Certificate

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C365S049130, C365S233100

Reexamination Certificate

active

11362694

ABSTRACT:
An integrated circuit device includes a first latch having a first input to receive a first predecode value, a second input to receive a first clock signal, and an output to provide a latched first predecode value responsive to an edge event of the first clock signal. The integrated circuit device further includes a memory component. The memory component includes an input to receive the latched first predecode value and the latched second predecode value, a first bit line, and a plurality of word lines coupled to the first bit line. Each word line is associated with a corresponding bit of the latched second predecode value. The integrated circuit device further includes logic having an input to receive the corresponding bit of the latched first predecode value. The logic is to precharge the first bit line directly responsive to only a value at the corresponding bit of the latched first predecode value.

REFERENCES:
patent: 4627032 (1986-12-01), Kolwicz et al.
patent: 4727519 (1988-02-01), Morton et al.
patent: 5077693 (1991-12-01), Hardee et al.
patent: 5566108 (1996-10-01), Kitamura
patent: 5600605 (1997-02-01), Schaefer
patent: 5600606 (1997-02-01), Rao
patent: 5745421 (1998-04-01), Pham et al.
patent: 5754819 (1998-05-01), Lynch et al.
patent: 6061285 (2000-05-01), Tsukikawa
patent: 6205069 (2001-03-01), Kim
patent: 6813628 (2004-11-01), Bhushan et al.
Dhong et al., “A 4.8GHz Fully Pipelined embedded SRAM in the Streaming Processor of a CELL Processor,” ISSCC 2005/Session 26/Static Memory/26.7, 2005 IEEE International Solid-State Circuits Conference, pp. 486-487 and 612.
Ebergen et al., “GasP Control for Domino Circuits,” IEEE, Proceedings of the Eleventh International Symposium on Advanced Research in Asynchronous Circuits and Systems, New York City, Mar. 13-16, 2005, pp. 12-22.
Wuu et al., “The Asynchronous 24MB On-Chip Level-3 Cache for a Dual-Core Itanium-Family Processor,” ISSCC 2005/Session 26/ Static Memory/ 26.8, 2005 IEEE International Solid-State Circuits Conference, pp. 488-489 and 618.
Cortadella, J., et al., “Evaluating ″A+B=K″Conditions in Constant Time,” IEEE ISCAS, 1998, pp. 243-246.
Cortadella, J., et al., “Evaluation of A+B=K Conditions Without Carry Propagation,” IEEE Transactions on Computers, vol. 41, No. 11, Nov. 1992, pp. 1484-1488.
Heald, K., et al., “64-KByte Sum-Addressed-Memory Cache with 1.6-ns Cycle and 2.6-ns Latency,” IEEE Journal of Solid-State Circuits, vol. 33, No., 11, Nov. 1998, pp. 1682-1689.
Lee, Y., et al., “Address Addition and Decoding without Carry Propagation,” IEICE Trans. Inf. & Syst., vol. E80-D, No. 1, Jan. 1997, pp. 98-100.
Lynch, W., et al., “Low Load Latency through Sum-Addressed Memory (SAM).” Sun Microsystems, 11 pages, 1998.

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