Bit line landing pad and borderless contact on bit line stud...

Details Bit line landing pad and borderless contact on bit line stud... Bit line landing pad and borderless contact on bit line stud...

2000-10-30

2002-02-26

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S253000

Reexamination Certificate

active

06350649

ABSTRACT:

BACKGROUND OF THE INVENTION
In order to make more efficient use of integrated circuit surface area, conventional two-dimensional semiconductor technology has evolved such that contemporary circuits are formed on multiple layers in a three-dimensional configuration. In such configurations, active devices and interconnects are formed in a layered relationship. During the formation of each subsequent layer, an inter-layer pathway, referred to in the art as a “plug”, or “stud” is electrically coupled between the various active devices and transmission lines of the different layers. To assist in aligning a plug, “landing pads” or “taps” are formed in lower layers to serve as a target for the plugs passing from the upper layer. The landing pads are coupled to an underlying circuit or interconnect and are generally larger in surface area than the circuit or interconnect to serve as a wider-tolerance target for the plug.
Such multi-layered technology has enabled the design of highly-integrated memory devices, for example DRAM devices, having extremely high capacity, for example above 1 gigabyte. Such DRAM devices include multiple arrays of memory cells, densely and efficiently laid out under tight design constraints. Between the cell areas are peripheral regions, which include supporting circuitry and interconnect circuitry between the cells, as well as input/peripherals, and the like.
Any misalignment between the vertical plugs and the horizontal interconnect features can cause defects and reliability problems. To ensure that the plug aligns with a feature, the features are made larger than required, for example through the use of landing pads. The area by which the feature is made larger is referred to in the art as a “border” around the vertical contact hole. Any excessive border area thus has a negative impact on circuit density.
Attempts have been made in the past to provide multiple layer interconnect, while reducing or eliminating the border area. These include circuits and fabrication procedures disclosed in U.S. Pat. Nos. 6,083,824, 5,612,254, and 4,966,870.
To a larger extent, the packing density of circuits is limited by how closely the interconnect metal between circuits can be formed without encroaching on each other. These limits are dictated by design rules that govern the separation of one level of contact from another, and by design rules for nesting tolerance or for borders used around contacts.
Other efforts have made toward reducing the high-aspect ratio of the holes made for inter-level interconnects, where the aspect ratio refers the height of a hole as compared to its width. In general, the deeper the hole, the more difficult it is to fabricate the hole. Using the line of an underlying circuit, for example a bit line of a DRAM memory device, as a landing pad, the aspect ratio of the interconnection hole can be significantly reduced.
A typical multiple-layer DRAM memory device
20
is illustrated in FIG.
1
. The memory device includes a cell region
22
and a peripheral region
24
. The cell region
22
includes active switching devices, coupled to vertically-oriented capacitors
28
, that serve as data storage devices. A cell bit line
26
serves as an interconnect to transfer data between peripheral circuit regions and the cell region
22
. The peripheral region
24
includes a number of bit lines
32
, that function as local interconnects, or studs, electrically coupling between the various active devices and transmission lines of the different layers. An insulative oxide layer
38
is formed above the bit lines
32
, and an interconnect stud
34
is opened through the oxide layer and connected to the bit line
32
.
When the bit lines
32
are used for local interconnection, for example especially in sense amplifier regions, the layers of circuits can become very dense and crowded. For example, to access the bit line
32
from an upper layer, the region
30
between the bit lines must be accurately etched to form a stud interconnect hole; both in a lateral direction, so as to avoid contact with adjacent bit lines, and in a vertical direction, so as to ensure that the hole is formed at the proper depth. Because the peripheral region
24
, for example a sense amplifier region of a DRAM device, is often times densely populated with various interconnect paths, the cross-sectional area of any vertical stud interconnects should be minimized. Therefore, the above case requires subsequent formation of high-aspect-ratio studs that are difficult to achieve using contemporary fabrication processes.
Contemporary techniques of forming the interconnect stud are subject to several process limitations. These include horizontal misalignment, in a lateral direction, where the stud hole may be laterally misaligned with the underlying bit line during formation of the stud hole. Vertical misalignment can also occur, wherein the stud hole is not etched deep enough, so the stud does not make contact with the underlying bit line, or wherein the stud hole is etched too deeply, and is etched through the bit line, as shown in region
36
of FIG.
1
.
To improve alignment accuracy, U.S. Pat. No. 5,895,239 discloses a technique for employing a bit line landing pad together with a bit line stud. However, this approach requires tight tolerances at either, or both, the top portions of the bit lines, including the landing pad, and bottom portions of the upper interconnect stud, so as to provide a minimal width at the top of the bit line, and a maximum width at the bottom of the upper interconnect stud. A wide stud top limits circuit density considerations, while a narrow stud bottom leads to increased contact resistance and an increased aspect ratio that is difficult to accurately fabricate. No provision is made for vertical alignment of the stud, so if the stud hole is slightly misaligned with the underlying bit line, a void can be formed in the underlying inter-layer dielectric adjacent the stud.
Another approach at multiple-layered interconnect is disclosed in U.S. Pat. No. 5,891,799. In this approach, an etch-stop layer, for example a silicon nitride masking layer (Si
3
N
4
) is formed over an inter-layer dielectric (SiO
2
). Stud holes are patterned in the mask layer and underlying dielectric layer for the deposit of studs to connect to the lower layer. Once the studs are formed, the masking layer later serves as an etching reference for eventual formation of landing pads for studs formed through an upper layer. However, this technique suffers from a number of limitations. Since the Si
3
N
4
masking layer is a high-stress-bearing material, and is formed indiscriminately as a layer over the entire circuit, this configuration imparts undue stress on the various layers, which may lead to warping of the circuit. Additionally, due to its high density, the masking layer prevents outgassing of impurities contained in the inter-layer dielectric, for example C, F, and Cl, during later high-temperature processes. The remaining Si
3
N
4
masking layer would prevent the introduction of H
2
and O
2
during popular alloy processes, greatly affecting the conductive adhesiveness between the upper and lower metals and defect curing efficiency.
Furthermore, this process is incompatible with contemporary memory fabrication processes, because the Si
3
N
4
masking layer would be applied between bit lines. With reference again to
FIG. 1
, dielectric spacers
40
A,
40
B are formed on each lateral side of cell bit line
26
A prevent shorting between the cell bit line
26
A and the capacitor
28
. In order to make such spacers
40
A, it would be necessary to remove any masking layer between adjacent bit lines
26
A,
26
B to allow for space for the capacitors
28
to be inserted between the bit lines
26
A,
26
B. However, this process would also remove any dielectric layer
42
A,
42
B formed over the bit lines
26
A,
26
B necessary for insulating the bit lines
26
A,
26
B from the capacitors. This would also remove any masking layer on either side of the peripheral region bit lines
32
, defeating the

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