Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2001-03-19
2002-12-31
Fabrny, Jr., Wael (Department: 2823)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S253000, C257S776000, C257S304000
Reexamination Certificate
active
06500706
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The present invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of eliminating coupling capacitance between bit-lines in a stack DRAM cell with capacitor under bit-line (CUB) in the fabrication of integrated circuits.
(2) Description of the Prior Art
The popular 1-transistor (1T) dynamic random access memory (DRAM) cell is composed of a pass transistor (for switching) and a storage capacitor. The state-of-the-art DRAM cell has typically either a stacked capacitor or a trench capacitor; referred to as “stack cell” or “trench cell”, respectively. Among stack cells, the capacitor can be fabricated either above or below the bit-line, referred to as Capacitor Over Bit-line (COB) or Capacitor Under Bit-line (CUB) structures. All of these cell structures are popular in current manufacture of 16 Mb and 64 Mb DRAM. U.S. Pat. No. 6,048,767 to Terada and U.S. Pat. No. 5,700,731 to Lin et. al. disclose COB schemes.
In integrated circuit manufacture, embedded dynamic random access (DRAM) devices have both memory cells and logic cells formed on a single silicon chip. The stack DRAM with CUB is preferred for embedded DRAM applications, since capacitors can be fabricated before logic transistors (for avoiding thermal cycle effect on logic transistors) and the metal bit-line can be shared with logic circuits. The conventional bit-lines of stack DRAM with CUB scheme are fabricated at the same metal level (e.g. M
1
) with minimum line and spacing design rules. U.S. Pat. No. 5,893,734 to Jeng et al discloses such a scheme. There is coupling capacitance within each bit-line pair (BL and BL-bar) as well as from adjacent bit-lines. The stack cell with CUB scheme indeed has drawbacks of larger bit-line to bit-line coupling noise (See “A New DRAM Cell Structure with Capacitor-Equiplanar-to-Bitline (CEB) for Bit-line Coupling Noise Elimination” by L. Chang et al, 1998
International Conference on Solid
-
State and Integrated-Circuit Technology
(ICSICT'98), p. 428-431, October 1998) and larger cell size than the stack cell with COB scheme, based on the same design rules. For these reasons, the COB scheme is preferred by stand-alone or commodity DRAM (See “DRAM Technology Perspective for Gigabit Era” by K. Kim et al,
IEEE Transactions Electron Devices
, V. 45, No. 3, p. 598-608, 1998 and “Limitations and Challenges of Multi-gigabit DRAM Chip Design” by K. Itoh et al,
IEEE Journal of Solid
-
State Circuits
, V. 32, No. 5, p. 624-634, 1997), although the CUB scheme is preferred by embedded DRAM applications.
There are conventional ways for bit-line coupling noise reduction, e.g. using twisted bit-line. Some of these methods are disclosed in “Twisted Bit-line Techniques for Multi-gigabit DRAMs” by D. Min et al,
IEE Electronics Letters
, V. 33, No. 16, P. 1380, 1997 and “Twisted Bit-line Architectures for Multi-megabit DRAMs” by H. Hidaka et al,
IEEE Journal of Solid
-
State Circuits
, V. 24, No. 1, p. 35-42, 1989. U.S. Pat. No. 6,140,704 to Kang et al and U.S. Pat. No. 5,625,585 to Ahn et al show twisted bit-line layouts. One drawback of the twisted bit-line technique is its larger size for implementation. However, in the embedded DRAM process, multi-layer metal is available for both logic and DRAM. Thus, the bit-line inter-connect can utilize multi-level metal for no increase of process complexity. A new bit-line interconnect scheme is proposed in which bit-lines are fabricated in an alternating manner at multiple metal layers.
SUMMARY OF THE INVENTION
Accordingly, it is a primary object of the present invention to provide an effective and very manufacturable method for forming a stack DRAM cell with capacitor under bit-line (CUB) in the fabrication of integrated circuits.
It is a further object of the invention to provide a process for forming a stack DRAM cell with CUB wherein coupling noise is eliminated.
Another object is to provide a process for forming a stack DRAM cell with CUB for use in stand-alone or embedded DRAM wherein coupling noise is eliminated.
Yet another object is to provide a process for forming a stack DRAM cell with CUB wherein coupling noise is eliminated by alternating metal levels by bit-line pairs.
A further object is to provide a process for forming a stack DRAM cell with CUB wherein coupling noise is eliminated by alternating metal levels by each bit-line.
A still further object is to provide a process for forming a stack DRAM cell with CUB wherein coupling noise is eliminated by alternating metal levels within a bit-line.
Yet another object is to provide a process for forming a stack DRAM cell with CUB wherein coupling noise is eliminated by alternating metal levels by bit-line pairs with metal shielding between bit-lines.
Another further object is to provide a process for forming a stack DRAM cell with CUB wherein coupling noise is eliminated by alternating metal levels by each bit-line with metal shielding between bit-lines.
Another still further object is to provide a process for forming a stack DRAM cell with CUB wherein coupling noise is eliminated by alternating metal levels within a bit-line with metal shielding between bit-lines.
In accordance with the objects of the invention, a method for forming a stack DRAM cell with CUB wherein coupling noise is eliminated is achieved. A capacitor node contact junction and a plurality of bit-line junctions are provided in a semiconductor substrate. A capacitor is formed overlying the semiconductor substrate and connected to the capacitor node contact junction by a contact plug through a first insulating layer. A second insulating layer is deposited overlying the capacitor. A plurality of metal plugs is formed through the second and first insulating layers each contacting one of the plurality of bit-line junctions. Now, bit-lines are formed according to one of three methods.
In a first method, bit-lines are formed each contacting one of the plurality of metal plugs wherein a first pair of bit-lines is fabricated in a first metal layer overlying the second insulating layer and wherein a second pair of bit-lines is fabricated in a second metal layer separated from the first metal layer by a third insulating layer and wherein the second pair of bit-lines contacts one of the metal plugs by a via plug through the third insulating layer and wherein the first pair of bit-lines is horizontally spaced from the second pair of bit-lines.
In a second method, bit-lines are formed, each contacting one of the plurality of metal plugs wherein a first of each pair of bit-lines is fabricated in a first metal layer overlying the second insulating layer and wherein a second of each pair of bit-lines is fabricated in a second metal layer separated from the first metal layer by a third insulating layer and wherein the second of each pair of bit-lines contacts one of the metal plugs by a via plug-through the third insulating layer and wherein the first of each pair of bit-lines is horizontally spaced from the second of each pair of bit-lines.
In a third method, bit-lines are formed, each contacting one of the plurality of metal plugs wherein each bit-line is divided into segments and wherein first segments of a bit-line are fabricated in a first metal layer overlying the second insulating layer and wherein alternating segments of the bit-line are fabricated in a second metal layer separated from the first metal layer by a third insulating layer and wherein for each pair of bit-lines, facing segments of a first and second of the bit-line pair are fabricated in different metal layers and wherein the segments of each bit-line in the second metal layer contact one of the metal plugs by a via plug through the third insulating layer and wherein the first of each pair of bit-lines is horizontally spaced from the second of each pair of bit-lines. This completes fabrication of a DRAM with capacitor under bit-line (CUB) cell in an integrated circuit device.
REFERENCES:
patent: 5014110 (1991-05-01), Satoh
patent: 5107459 (1992-04-01), Chu et al.
pat
Ackerman Stephen B.
Fabrny, Jr. Wael
Pike Rosemary L. S.
Saile George O.
Taiwan Semiconductor Manufacturing Company
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