Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2002-02-15
2003-12-30
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C257S370000
Reexamination Certificate
active
06670229
ABSTRACT:
TECHNICAL FIELD
The present invention relates to a bipolar transistor produced by processes employed in the manufacture of CMOS nonvolatile memory devices, and in particular to a circuit comprising a high gain vertical transistor. In addition, it relates to the manufacturing process of a bipolar transistor produced by means of the processes employed in the manufacture of CMOS nonvolatile memory devices.
BACKGROUND OF THE INVENTION
In some circuit applications it is desirable to insert bipolar transistors into CMOS type integrated digital circuits.
Further, for more economical construction of such integrated circuits, it is desirable to have a manufacturing process in which both the bipolar transistors and the CMOS transistors are formed using the same masks and with a minimum number of process phases.
There are known methods for producing bipolar transistors integrated into CMOS circuits at low voltage, using substantially the same process phases. These devices, however, provide very low current gains, usually on the order of a few tens.
SUMMARY OF THE INVENTION
An embodiment of the present invention produces a bipolar transistor with a much higher current gain, using processes commonly employed to manufacture CMOS nonvolatile memories, without adding new process phases.
The bipolar transistor is produced by processes used in the manufacture of nonvolatile memory CMOS devices, and includes: a semiconductor substrate having a first type of conductivity, at least one PMOS transistor formed within said substrate, at least one NMOS transistor formed within said substrate, and a bipolar transistor. The bipolar transistor includes a buried semiconductor layer having a second type of conductivity placed at a prefixed depth from the surface of said bipolar transistor, an isolation semiconductor region having a second type of conductivity, in direct contact with said buried semiconductor layer, and suitable for delimiting a portion of said substrate to form a base region, an emitter region of said transistor formed within said base region, having a second type of conductivity, a base contact region of said transistor formed within said base region, having a first type of conductivity, a collector contact region of said transistor formed within said isolation semiconductor region, having a second type of conductivity, wherein said base region has a doping concentration of between 10
16
and 10
17
atoms/cm
3
.
An embodiment of the present invention forms a bipolar transistor simultaneously and with the same processes as those used to manufacture nonvolatile memory CMOS devices having a gate region, a source region and a drain region. The method includes: forming a buried semiconductor layer having a second type of conductivity, within a substrate having a first type of conductivity, simultaneously to the formation of a similar layer of buried semiconductor for an N-type CMOS device; forming an isolation semiconductor layer having a second type of conductivity, in direct contact with said semiconductor buried layer, and adapted to delimit a portion of said substrate, forming the base region, simultaneously to the formation of the N-well area of a P-type CMOS device; forming an emitter region and a collector contact region respectively in said base region and in said isolation semiconductor layer, both having a second type of conductivity, simultaneously to the formation a similar semiconductor layer for said source and drain regions of said N-type CMOS devices; and forming a base contact region of said transistor in said base region, having a first type of conductivity, simultaneously to the formation of a similar layer of semiconductor for said source and drain regions of said P-type CMOS devices.
Thanks to the present invention it is possible to realize a high gain bipolar transistor using substantially the same process phases as those used for high voltage CMOS devices, particularly those used in circuits for nonvolatile memories.
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Ghezzi Paolo
Vendrame Loris
Iannucci Robert
Jorgenson Lisa K.
Nelms David
Seed IP Law Group PLLC
STMicroelectronics S.r.l.
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