Barrier layer for electroplating processes

Details Barrier layer for electroplating processes Barrier layer for electroplating processes

1999-08-16

2001-12-11

Wong, Edna (Department: 1741)

Electrolysis: processes, compositions used therein, and methods

Electrolytic coating

Forming nonelectrolytic coating before depositing...

C205S184000, C205S170000, C205S176000, C205S224000, C205S227000, C427S372200, C427S124000, C427S248100, C427S250000

Reexamination Certificate

active

06328871

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to electrochemical deposition or electroplating a metal onto a substrate. More particularly, the present invention relates to methods of forming a barrier layer and a seed layer prior to filling the structures formed on a substrate using an electroplating process.
2. Background of the Related Art
Copper has become a choice metal for filling sub-micron, high aspect ratio interconnect features on substrates as circuit densities increase for the next generation of ultra large scale integration because copper and its alloys have lower resistivities and significantly higher electromigration resistance as compared to aluminum. These characteristics are important for supporting the higher current densities experienced at high levels of integration and increased device speed.
The aspect ratio for the features, i.e., the ratio of the feature height to the feature width, increases with higher levels of integration. Many traditional deposition processes have difficulty filling structures where the aspect ratio exceeds 4:1, and particularly where it exceeds 10:1 and is less than 0.25 &mgr;m wide. Therefore, there is a great amount of ongoing effort being directed at the formation of void-free, sub-micron high aspect ratio features. Additionally, as the feature widths decrease, the interconnect features experience increased current densities that require good, void-less formation of the metal within the interconnect feature.
Despite the desirability of using copper for semiconductor device fabrication, choices of fabrication methods for depositing copper into very high aspect ratio features are limited because common chemical vapor deposition processes and physical vapor deposition processes have provided unsatisfactory results for forming voidless metallization of sub-micron high aspect ratio interconnect features. As a result, electroplating or electrochemical deposition is becoming an accepted method for copper metallization of interconnect features on semiconductor devices.
FIGS. 1A-1E
illustrate a typical metallization technique for forming interconnect features in a multi-layered substrate
10
. Generally, the method comprises physical vapor depositing a barrier layer over the feature surfaces, physical vapor depositing a conductive metal seed layer, preferably copper, over the barrier layer, and then electroplating a conductive metal, preferably copper, over the seed layer to fill the interconnect structure/feature. Finally, the deposited layers and the dielectric layers are planarized, such as by chemical mechanical polishing (CMP), to define a conductive interconnect feature.
FIGS. 1A through 1E
are cross sectional views of a substrate
10
having multi-layered structures including a dielectric layer
12
formed over an underlying layer
14
which contains an electrically conducting feature
16
. The underlying layer
14
may take the form of a doped silicon substrate or it may be a first or subsequent dielectric/insulating layer formed on a substrate. The dielectric layer
12
is formed over the underlying layer
14
in accordance with procedures known in the art, such as dielectric CVD, to form a part of the overall integrated circuit. Once deposited, the dielectric layer
16
is patterned and etched to form interconnect features, such as vias, contacts and lines. Etching of the dielectric layer
12
can be accomplished using various generally known dielectric etching processes, including plasma etching. Although a dual damascene structure and a connection line are illustrated in
FIGS. 1A-1E
, other types of interconnect features are typically metallized using this technique as well.
Referring to
FIG. 1A
, a partial cross-sectional diagram of a substrate
10
is shown having a dual damascene structure
18
and a connection line
20
patterned and etched in the dielectric layer
12
. The dual damascene structure
18
typically comprises a via portion
21
and a trench portion
25
. The via portion
21
of the dual damascene structure
18
is defined by a via floor
22
exposing at least a portion of the conductive feature
16
and lower sidewalls
24
. The trench portion
25
of the dual damascene structure
18
is defined by the step surfaces
26
and upper sidewalls
28
.
FIG. 1A
also shows a connection line
20
which is typically formed through a groove on the surface of the dielectric layer
12
that provides electrical connections across the surface of the dielectric layer
12
to other structures and/or devices. The connection line
20
is defined by a line bottom surface
30
and line sidewalls
32
etched in the dielectric layer
12
.
Referring to
FIG. 1B
, a barrier layer
34
, preferably comprising tantalum (Ta) or tantalum nitride (TaN), is deposited over the surface of the substrate
10
, including the surfaces of the dual damascene structure
18
and the connection line
20
. The barrier layer is typically deposited using physical vapor deposition (PVD) by sputtering a tantalum target in an argon plasma or by reactive physical vapor deposition by sputtering a tantalum target in a nitrogen/argon plasma. Other deposition processes, such as chemical vapor deposition (CVD) or combination of CVD/PVD, may be used to deposit the barrier layer for improved texture and film properties. The barrier layer limits the diffusion of copper into the semiconductor substrate and the dielectric layer and thereby dramatically increases the reliability of the copper interconnect features. It is preferred that the barrier layer has a thickness between about 25 Å and about 400 Å, most preferably about 100 Å.
Referring to
FIG. 1C
, a copper seed layer
36
is deposited over the barrier layer
34
using PVD. Other metals, particularly noble metals, can also be used for the seed layer. The copper seed layer
36
provides good adhesion for a subsequently deposited copper layer.
Referring to
FIG. 1D
, a copper layer
38
is electroplated over the copper seed layer
36
to metallize the dual damascene structure
18
and the line connection
20
. However, the electroplating metallization process presently practiced typically forms voids
40
in the interconnect features that may lead to defective devices or premature breakdown of the devices, as discussed in more detail below.
Referring to
FIG. 1E
, the top portion of the processed substrate
10
, i.e., the exposed copper layer
38
, is then planarized, preferably by chemical mechanical polishing (CMP). During the planarization process, portions of the copper layer
38
, copper seed layer
36
, barrier layer
34
, and a top surface of the dielectric layer
12
are removed from the top surface of the substrate, leaving a fully planar surface with conductive interconnect features, such as the dual damascene structure
18
and connection line
20
.
Metal electroplating in general is a well known art and can be achieved by a variety of techniques. Present designs of cells for electroplating a metal onto a substrate are generally based on a fountain plater configuration. In the fountain plater configuration, the semiconductor substrate is positioned above a cylindrical electrolyte container with the plating surface facing an opening of the cylindrical electrolyte container. The electrolyte is pumped to flow upwardly and contact the substrate plating surface. The substrate is electrically biased and connected as the cathode of the plating system, and the surfaces to be plated are electrically connected to the cathode power source to provide the electrical current that induces the metal ions in the plating solution to deposit onto the exposed conductive surface of the substrate. An anode is typically disposed in the electrolyte and electrically biased to attract the negatively charged counterparts of the metal ions in the electrolyte. The fountain plater is generally adequate for electroplating large, low aspect ratio features (i.e., larger than micrometer-sized and lower than 1:1 height to width ratio). However, a number of obstac

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