Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2003-04-18
2004-11-16
Pham, Long (Department: 2814)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S613000, C438S618000, C257S735000, C257S778000
Reexamination Certificate
active
06818538
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to semiconductor packaging technology, and more particularly, to a ball grid array (BGA) semiconductor package and method of fabricating the same, which can be used for the fabrication of a BGA package, and which can help prevent the fabricated BGA package from having voids in the package body thereof to thereby ensure the quality of the BGA package.
2. Description of Related Art
BGA (Ball Grid Array) is an advanced type of semiconductor packaging technology which is characterized by the use of a substrate as chip carrier whose front side is used for mounting one or more semiconductor chips and whose back side is provided with a grid array of solder balls. During SMT (Surface Mount Technology) process, the BGA package can be mechanically bonded and electrically coupled to an external printed circuit board (PCB) by means of these solder balls.
FIG.
1
A and
FIG. 1B
respectively show a sectional view and a top view of a conventional BGA package. As shown, this BGA package comprises: (a) a substrate
10
; (b) a ground pad
20
; (c) a solder mask
30
; (d) a semiconductor chip
40
; (e) an electrically-conductive layer (such as silver paste)
50
; (f) a set of bonding wires (such as gold wires)
60
; (g) an encapsulation body
70
; (h) a plurality of electrically-conductive vias, including a group of ground/heat-dissipation vias
81
and a group of power/signal vias
82
; and (i) a grid array of solder balls, including a group of ground/heat-dissipation balls
91
and a group of power/signal vias
92
.
The chip
40
is electrically coupled to the ground/heat-dissipation balls
91
successively by way of the silver paste layer
50
, the ground pad
20
, and the ground/heat-dissipation vias
81
, so as to be electrically coupled to the ground/heat-dissipation structure on an external printed circuit board (not shown) by way of the ground/heat-dissipation vias
81
.
One drawback to the foregoing BGA package, however, is that voids
51
would exist in the silver paste layer
50
filled in the opening
31
of the solder mask
30
, which would undesirably cause a popcorn effect during subsequent reflow process under a high temperature condition. This popcorn effect would break apart the encapsulation body, causing the BGA package to become defective.
The cause of the existence of the voids
51
is depicted in
FIGS. 2A-2C
. As shown in
FIG. 2A
, during the die-attachment process, an adhesive agent, such as silver paste, is coated over the surface of the solder mask
30
to form the silver paste layer
50
; and then as shown in FIG.
2
B and
FIG. 2C
, the chip
40
is forcefully pressed down against the silver paste layer
50
, thus urging the silver paste layer
50
to spread out over the die-attachment area. During this process, however, since the overall width of the chip
40
is located directly above the opening
31
in the solder mask
30
, it would undesirably trap the air in the opening
31
, thus resulting in the forming of voids
51
therein. The existence of these voids
51
would undesirably cause a popcorn effect during subsequent reflow process under a high temperature condition. This popcorn effect would break apart the encapsulation body, causing the BGA package to become defective.
Related patents includes, for example, the following patents:
U.S. Pat. No. 5,545,923 “SEMICONDUCTOR DEVICE ASSEMBLY WITH MINIMIZED BOND FINGER CONNECTIONS”;
U.S. Pat. No. 5,703,402 “OUTPUT MAPPING OF DIE PAD BONDS IN A BALL GRID ARRAY”.
The foregoing patents, however, provide no solutions to the aforementioned problem, and therefore it cannot be used to eliminate the popcorn effect to help ensure the quality of the BGA package. There exists therefore a need in the semiconductor industry for a new semiconductor packaging technology that can eliminate the popcorn effect due to existence of voids in the BGA package.
SUMMARY OF THE INVENTION
It is therefore an objective of this invention to provide a new BGA semiconductor packaging technology that can eliminate the popcorn effect due to existence of voids in the BGA package.
The BGA semiconductor packaging technology according to the invention comprises the following steps: preparing a substrate having a predefined die-attachment area on one surface thereof; (2) forming a ground pad over the die-attachment area on the substrate; (3) forming a solder mask over the ground pad, wherein the solder mask is formed with at least one opening to expose one portion of the ground pad, and wherein the opening is located in such a manner that a fraction of the overall width of the opening is located beyond the die-attachment area; (4) pasting an adhesive agent over the solder mask; and (5) pressing at least one semiconductor chip forcefully against the adhesive agent over the solder mask, causing the adhesive agent over the solder mask to spread out sideways and fill into the opening in the solder mask to expel the air in the opening through the gap above the opening to the atmosphere.
The BGA semiconductor packaging technology according to the invention is characterized in that openings of a solder mask are formed on a given edge of a die attachment area, and entire or partial width of each opening is disposed outside the die attachment area. Accordingly, air within the opening of the solder mask is sufficiently eliminated during die bonding process, so as to prevent void formation as adhesive is filled into the opening. Therefore, in the follow-up steps, high temperature in reflowing process will not cause popcorn as in the prior-art, so as to remain good quality of the semiconductor package.
REFERENCES:
patent: 6650019 (2003-11-01), Glenn et al.
Chen Chin Te
Chiang Kuo-Chu
Lai Yu-Ting
Corless Peter F.
Edwards & Angell LLP
Jensen Steven M.
Pham Long
Siliconware Precision Industries Co. Ltd.
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