Non-volatile memory cell techniques

Details Non-volatile memory cell techniques Non-volatile memory cell techniques

2002-05-21

2004-11-09

Phan, Trong (Department: 2818)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185270, C365S185280, C365S185290

Reexamination Certificate

active

06816412

ABSTRACT:

BACKGROUND OF THE INVENTION
This invention relates to memory cells and more particularly relates to non-volatile memory cells.
Non-volatile memory cells maintain their contents without the need for an external power supply. In comparison, SRAM, DRAM or other memory technologies lose their contents when the power is switched off. An internal battery is sometimes used to mimic non-volatile memory with SRAM or DRAM; however, an internal battery installation is expensive and cannot guarantee proper operation over long periods of time. It is highly desirable to store certain data, such as boot-up code, chip ID, chip self-repair information, etc., in a non-volatile memory.
The application of non-volatile memory in the price-competitive application specific integrated circuit (ASIC) market has been limited due to the complex processes required to fabricate these memories. Non-volatile memory fabrication requires numerous extra mask layers and fabrication steps, which increase cost and decrease yields. High cost and complex processing has been a barrier for using embedded non-volatile memory in the ASIC market. The information typically is stored on a floating storage polysilicon node. The floating node potential is controlled by a second polysilicon gate coupled to the storage polysilicon gate. A majority of the extra cost for non-volatile memories is incurred in achieving this double polysilicon structure separated by a thin oxide layer.
Non-volatile memory needed on ASIC's has been provided on a circuit board as a separate chip which is manufactured by specialized fabrication processes. The availability of non-volatile memory in standard generic digital CMOS processes would cut board-level cost and open up a range of new embedded applications.
U.S. Pat. No. 6,215,148 (the “'148 patent”) describes a non-volatile memory cell that avoids double polysilicon gate structure. However, the '148 patent structure creates other problems described at Col. 2, lines 36-45. The '148 patent also describes an attempt to avoid the problems by increasing the complexity of the cell as shown in FIGS. 4A and 4B. These problems are overcome by the embodiments described in this specification.
Further limitations and disadvantages of conventional and traditional approaches will become apparent to one of skill in the art, through comparison of such systems with the present invention as set forth in the remainder of the present application with reference to the drawings.
BRIEF SUMMARY OF THE INVENTION
According to an apparatus embodiment of the invention, a non-volatile memory cell comprises a node arranged to store charge. An electrically insulating first layer is coupled between the node and a source of a first voltage. An electrically insulating second layer is coupled between the node and a source of a second voltage, and the area of the first layer being smaller than the area of the second layer. A controller is arranged to cause the first voltage to be greater than the second voltage so that charge is extracted from the node and arranged to cause the second voltage to be greater than the first voltage so that charge is injected into the node.
One method embodiment of the invention is useful in a non-volatile memory cell comprising a node arranged to store charge that generates a node voltage. In such an environment, charge on the node is adjusted by a method comprising capacitive coupling a first voltage to the node and capacitive coupling a second voltage less than the first voltage to the node, the capacitive coupling of the first voltage being less than the capacitive coupling of the second voltage so that charge is extracted from the node. The method also comprises capacitive coupling a third voltage to the node and capacitive coupling a fourth voltage to the node greater than the third voltage, the capacitive coupling of the third voltage being less than the capacitive coupling of the fourth voltage so that charge is injected into the node.
By using the foregoing techniques, charge may be adjusted in a non-volatile memory with a degree of economy, ease of fabrication and reliability previously unattained.
These and other advantages and novel features of the present invention, as well as details of an illustrated embodiment thereof, will be more fully understood from the following description and drawings.


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