Automatic shutdown or throttling of a bist state machine...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Reexamination Certificate

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C714S745000

Reexamination Certificate

active

07458000

ABSTRACT:
A Built-In-Self-Test (BIST) state machine providing BIST testing operations associated with a thermal sensor device(s) located in proximity to the circuit(s) to which BIST testing operations are applied. The thermal sensor device compares the current temperature value sensed to a predetermined temperature threshold and determines whether the predetermined threshold is exceeded. A BIST control element suspends the BIST testing operation in response to meeting or exceeding said predetermined temperature threshold, and initiates resumption of BIST testing operations when the current temperature value normalizes or is reduced. A BIST testing methodology implements steps for mitigating the exceeded temperature threshold condition in response to determining that the predetermined temperature threshold is met or exceeded. These steps include one of: ignoring the BIST results of the suspect circuit(s), or by causing the BIST state machine to enter a wait state and adjusting operating parameters of the suspect circuits while in the wait state.

REFERENCES:
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patent: 5961653 (1999-10-01), Kalter et al.
patent: 6496947 (2002-12-01), Schwarz
patent: 7103495 (2006-09-01), Kiryu
patent: 7260758 (2007-08-01), Agrawal et al.
patent: 2006/0064265 (2006-03-01), Kiryu
J. Barth, et al., “A 500MHz Multi-Banked Compilable DRAM Macro with Direct Write and Programmable Pipelining,”IEEE Journal of Solid-State Circuits, vol. 40, pp. 213-222, Jan. 2005.

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