Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2006-11-21
2006-11-21
Britt, Cynthia (Department: 2138)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S721000, C714S724000
Reexamination Certificate
active
07139957
ABSTRACT:
A multi-bit test value is loaded into a built-in latch of the IC component, and a pad of the component is selected for testing. A number of different sequences of test values are automatically generated, based on the stored test value, without scanning-in additional multi-bit values into the latch. A signal that is based on the different sequences of test values is driven into the selected pad and looped back. A difference between the test values and the looped back version of the test values is determined, while automatically adjusting driver and/or receiver characteristics to determine a margin of operation of on-chip I/O buffering for the selected pad.
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Ellis David G.
Gayles Eric S.
Gollapudi Eshwar
Khan Amjad
Querbach Bruce
Blakely , Sokoloff, Taylor & Zafman LLP
Britt Cynthia
Intel Corporation
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