Automatic generation of user definable memory BIST circuitry

Details Automatic generation of user definable memory BIST circuitry Automatic generation of user definable memory BIST circuitry

1997-08-21

1999-11-09

Teska, Kevin J.

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

39550007, 39550011, 714734, 714733, G06F 1750

Patent

active

059830093

ABSTRACT:
A method and apparatus are provided for automatically generating the design of a BIST for embedded memories of an IC. The approach relies on counters or pseudo-random generators for the implementation of many of the functions. The invention incorporates software that generates equations that can be used as inputs to a logic synthesis tool. The output of the synthesis tool feeds an automatic routing tool where it is merged with the output of the synthesis of the other portions of the integrated circuit, IC. The routing tool places and routes the signals through the logic described by the synthesis tool along with the remainder of the IC. The result is a completed IC design that includes efficient memory BIST circuitry.

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