Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2000-04-17
2003-11-25
Moise, Emmanuel L. (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S741000, C703S028000, C257S048000, C257S690000
Reexamination Certificate
active
06654919
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to silicon embedded testbenches generally and, more particularly, to inserting and reading probe points in silicon embedded testbenches.
BACKGROUND OF THE INVENTION
Conventional approaches for inserting and reading probe points in silicon embedded testbenches are not known. Conventional hardware emulation can have probe points. The probe points of conventional hardware emulation are not added via multiplexers to system on chip (SOC) busses at a module boundary in a systematic and automated way. Additionally, conventional probe points are not silicon embedded. Rather, the probe points are implemented. as field programmable gate arrays (FPGAs). Furthermore, hardware emulation does not provide embedded testbenches.
Co-pending application Ser. No. 09/400,686, filed Sep. 22, 1999, now U.S. Pat. No. 6,417,562, which is hereby incorporated by reference in its entirety, describes one solution for embedding testbenches in silicon. However, such an approach does not have a systematic method of adding probe points from simulation.
SUMMARY OF THE INVENTION
The present invention concerns a method for inserting and reading probe points in a silicon embedded testbench comprising the steps of (a) reading a simulation list of probe points, (b) enabling access to the list of probe points, (c) generating a core, and (d) displaying or comparing the probe points.
The objects, features and advantages of the present invention include providing a method and/or architecture for inserting and reading of probe points in silicon embedded testbenches that may (i) systematically embed probe point real-time and store state information programmed into silicon with a testbench; (ii) directly or indirectly embed probe point capability built from simulation probe point information; (iii) generate an extensive list of probe core generator parameters that may enable optimum access to probe points in silicon with minimal impact on design (e.g., including options for capture on changes only and/or capture at a specific time); (iv) automatically and/or quickly provide incremental builds to add or subtract probe points in terms of implementation in FPGAs; (v) provide testbenches embedded in silicon for verification of external SOC devices to have a model of a function that is not yet in silicon (e.g., to integrate entire SOC simulation environment models); (vi) provide an evaluation system to leverage embedded testbench probes, with menu programming for extracting probe information available from silicon; (vii) provide a testbench that may include loading up program memory of modules or chip under test; (viii) provide a testbench that may include loading simulation information either directly or indirectly in response to extracted probe information; and/or (ix) provide field diagnosis on issues that may be done with embedded testbenches with probe points accessible to the system with silicon.
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Lamarre Guy
LSI Logic Corporation
Moise Emmanuel L.
LandOfFree
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