Automated method of circuit analysis

Radiant energy – Inspection of solids or liquids by charged particles – Methods

Reexamination Certificate

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C250S309000

Reexamination Certificate

active

06288393

ABSTRACT:

FIELD OF THE INVENTION
The invention relates to integrated circuit imaging and analysis and more particularly to the use of an imaging system and a chemical analysis system for reverse engineering layers of integrated circuits.
BACKGROUND OF THE INVENTION
In the past, reverse engineering of circuits was a straightforward task. A circuit board was examined for traces providing a series of conductive connections between components. Circuit components were then analysed to determine connected elements and finally, a schematic of the board was entered for improvement, re-layout, or incorporation into a current design.
With the advent of MSI, LSI, and VLSI, this process became far more tedious. Initial attempts at reverse engineering integrated circuits relied on visual images of integrated circuit layers. Overlapping portions of a layer of an integrated circuit were photographed such that a portion of the layer is photographed. The images were developed as photographs and the photographs were assembled by hand in order to overlap adjacent images appropriately. Because of the redundant nature of integrated circuits, assembling the overlapping images into a single large composite image was difficult and required some skill.
Once a composite image was formed by taping or gluing the photographs together in an appropriate fashion, analysis of the images began. The analysis was performed by a skilled person in the art of reverse engineering or integrated circuit fault analysis who performed the steps of determining conductors, transistors, capacitors, resistors, etc. and forming a schematic of the circuit in dependence upon the analysis. Unfortunately, similarities of colour, contrast, and other output data provided by imaging systems used in reverse engineering, are often not determinative of similarity of material(s).
Reverse engineering a complex integrated circuit often represents several man months of effort and requires significant contribution by highly skilled individuals. Extraction of information requires skilled individuals to analyse images of layers and identify regions of particular materials based on experience and deduction. In essence, skilled individuals reconstruct layout information. Even though this approach is currently acceptable, it is very costly due to the time and effort required. For example, a single integrated circuit may comprise 10,000 images for a single layer. To analyse and infer information for each image is a very time consuming process.
It would be advantageous to automate some of the functions required to reverse engineer or analyse layers within an integrated circuit (IC).
PRIOR ART
In U.S. Pat. No. 4,623,255 in the name of Suszko and issued on Nov. 18, 1986, a Method of Examining Microcircuit Patterns is disclosed. The method comprises the steps of photographing a portion of an IC with dark field illumination and then developing the photograph. As described above, the mosaic formed by assembling photographs is time consuming and requires significant expertise.
In U.S. Pat. No. 5,086,477 in the name of Yu et al. and issued on Feb. 4, 1992, an Automated System for Extracting Design and Layout Information from an Integrated Circuit is disclosed. The system comprises an image capture means for capturing a plurality of images of an IC and a computer for assembling the images into a large mosaic by determining image overlap or by extrapolating images to fill gaps between adjacent images. Unfortunately, when working with current IC tolerances, gaps between abutting images may contain important circuit elements. Further the system taught by Yu et al. requires a known element to occur on each of several layers in order to align image composites for a multi-layer IC. The known element is identified by a skilled worker. Finding and identifying such an element on each layer of the IC is often time consuming. Also, removing an IC from the imaging system in order to prepare it for imaging successive layers, makes aligning successive layers automatically very difficult.
In U.S. Pat. No. 5,191,213 in the name of Ahmed et al. and issued on Mar. 2, 1993, an Integrated Circuit Structure Analysis method and apparatus are disclosed. An electron beam is directed toward successive layers of an IC. Some known problems with the use of electron beam scanning of IC layers are solved by Ahmed et al. but, reverse engineering of IC layers is not easily performed. Also, removing an IC from the imaging system in order to prepare it for imaging successive layers makes aligning successive layers in an automatic fashion very difficult.
In U.S. Pat. No. 5,694,481 in the name of Lam et al. and issued Dec. 2, 1997, a system for automatically constructing a mosaic of images using polygon extraction and filtering of images is disclosed. The method appears useful for imaging circuit information from SEM image data. The method disclosed presents no information on extracting chemical/circuit related information from the imaged IC. Unfortunately, a skilled individual using inference must perform further analysis of the layers. As such, the analysis is time consuming.
Scanning electron microscope (SEM) systems are known for use in imaging of integrated circuits. Using an SEM system, a beam of electrons is directed toward a surface to be imaged and scattered electrons from the surface are detected and analysed. The resulting information is used to determine an image. Because electrons are very small and beam energies are notable, electrons penetrate the surface and the image information that results is of the surface and details below the surface.
Focused ion beam (FIB) systems are known for use in several applications. FIB systems are useful in micromachining, imaging and etching. The use of FIB systems in imaging is well documented. In imaging, an ion beam is focused toward a location and backscattered ions are detected. Other particle emissions caused by collisions between ions within the beam and a surface being imaged may also be detected. Analysis of the detected particles results in an image. FIB systems are also used in etching. Etching with FIB systems began with applications for cutting traces in integrated circuits to allow for IC repair. With gas assisted etching, FIB systems provide a convenient system for etching away selected material from a surface of an IC in order to form holes of a desired depth.
Gas assisted etching is performed as follows. A reactive gas such as chlorine is fed into the FIB system near a surface of a substrate. The gas adsorbs to the surface approximating a monolayer. When the surface is scanned with ion beams, the energy of the ion beams is used to break chemical bonds, thus causing chemical reactions to proceed. As well as providing the energy needed to break bonds, the ions supply momentum to sputter the substrate. The chemical etching helps to enhance the physical sputtering of the ion beam. Another benefit is that the sputtered particles are volatilised and pumped away by a vacuum system forming part of the FIB systems.
Use of correct etchant gas significantly increases etching rate over FIB etching without an etchant gas. The increased etching rate is material dependent so selection of a gas for a particular material results in improved etching performance and improved control because of etching rate decreases when different material is exposed. These two advantages to gas assisted etching are known to allow etching of deep narrow holes.
Using a FIB system or a SEM system, information results in the form of images. These images, distinguish between different results using colour or intensity. FIB systems are particularly good for distinguishing between certain types of materials. Similarly, SEM systems are good at distinguishing certain types of materials. Some materials, though very different in nature, appear very similar in the images formed.
It would be advantageous to provide a method of imaging a layer within an integrated circuit to extract geometric information relating to regions within the layer wherein the information is based on the ch

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