Active solid-state devices (e.g. – transistors – solid-state diode – Test or calibration structure
Reexamination Certificate
2003-01-15
2008-10-14
Ha, Nathan W. (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Test or calibration structure
C257S620000
Reexamination Certificate
active
07435990
ABSTRACT:
An arrangement that will provide multiple communication paths for the simultaneously testing of a plurality of un-diced chips on a semiconductor wafer that will simultaneously permit each such communication path to service more than one chip while using a minimum number of tester contacts. These and other objects, features and advantages of the present invention are accomplished in a semiconductor wafer having thereon a number of kerf isolated integrated chips, each of said chips being coupled to at least two different ones of strategically placed administration circuits via two different stimulus buses; each chip being coupled to each administration circuit via selection control circuits laid down in the kerf area between the chips. It is this redundancy that significantly reduces the possibility of failure associated administration or selection control circuits. The stimulus busses can also be used to provide each chip with parallel serial scan data as well as power and other signals such as clock and enable and disable signals. Each chip control circuit provides the chip with power, bus clock, control, enable and response lines, can also connected to each chip via suitable lines in the kerfs.
REFERENCES:
patent: 5313158 (1994-05-01), Joosten et al.
patent: 5504369 (1996-04-01), Dasse et al.
patent: 5648661 (1997-07-01), Rostoker et al.
patent: 5899703 (1999-05-01), Kalter et al.
patent: 6228684 (2001-05-01), Maruyama
patent: 2002/0070429 (2002-06-01), Wester
patent: 2002/0190357 (2002-12-01), Kosugi et al.
patent: 02211648 (1990-08-01), None
patent: 06021174 (1994-01-01), None
Keller Brion L.
Koenemann Bernd K. F.
Lackey David E.
Wheater Donald L.
Ha Nathan W.
International Business Machines - Corporation
Thornton Francis J.
LandOfFree
Arrangement for testing semiconductor chips while... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Arrangement for testing semiconductor chips while..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Arrangement for testing semiconductor chips while... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3999178