Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2006-05-02
2006-05-02
Lebentritt, Michael (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S592000, C438S949000, C430S311000, C430S349000, C430S396000
Reexamination Certificate
active
07037791
ABSTRACT:
In accordance with the objects of this invention, a new method of fabricating a polysilicon gate transistor is achieved. An alternating aperture phase shift mask (AAPSM) is used to pattern polysilicon gates in a single exposure without a trim mask. A semiconductor substrate is provided. A gate dielectric layer is deposited. A polysilicon layer is deposited. The polysilicon layer, the gate dielectric layer and the semiconductor substrate are patterned to form trenches for planned shallow trench isolations (STI). A trench oxide layer is deposited filling the trenches. The trench oxide layer is polished down to the top surface of the polysilicon layer to complete the STI. A photoresist layer is deposited and patterned to form a feature mask for planned polysilicon gates. The patterning is by a single exposure using an AAPSM mask. Unwanted features in the photoresist pattern that are caused by phase conflicts overlie the STI. The polysilicon layer is etched to form the polysilicon gates.
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Hua-yu, Liu; Three Paths to Improved Critical dimension Control for Patterning 200nm to 100nm Transistor gates;Microelectronic Engineering 46 (199) pp. 41-45.
Chan Lap
Choo Lay Cheng
Lee James Yong Meng
Ackerman Stephen B.
Chartered Semiconductor Manufacturing Ltd.
Lebentritt Michael
Pike Rosemary L. S.
Pompey Ron
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