Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Flip chip
Reexamination Certificate
2001-03-22
2003-05-27
Donovan, Lincoln (Department: 2832)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Flip chip
C257S737000, C257S747000, C257S795000, C174S050510
Reexamination Certificate
active
06570259
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to microelectronic packaging of semiconductor chips and, more specifically, to IC flip chip assemblies designed to reduce the structural damage to C4 interconnections due to thermal stress and the CTE mismatch of the chip and the packaging material.
BACKGROUND OF THE INVENTION
Advances in microelectronics technology tend to develop chips that occupy less physical space while performing more electronic functions. Conventionally, each chip is packaged for use in housings that protect the chip from its environment and provide input/output communication between the chip and external circuitry through sockets or solder connections to a circuit board or the like. Miniaturization results in generating more heat in less physical space, with less structure for transferring heat from the package.
The heat of concern is derived from wiring resistance and active components switching. The temperature of the chip and substrate rises each time the device is turned on and falls each time the device is turned off.
As the chip and the substrate ordinarily are formed from different materials having different coefficients of thermal expansion (CTE), the chip and substrate tend to expand and contract by different amounts, a phenomenon known as CTE mismatch. This causes the electrical contacts on the chip to move relative to the electrical contact pads on the substrate as the temperature of the chip and substrate changes. This relative movement deforms the electrical interconnections between the chip and printed wiring board (PWB) and places them under mechanical stress. These stresses are applied repeatedly with repeated operation of the device, and can cause fatigue of the electrical interconnections. This is especially true for the solder ball of the controlled collapse chip connection, also known as “C4”, connections. It is therefore important to mitigate the substantial stress caused by thermal cycling as temperatures within the device change during operation.
One type of semiconductor chip package includes one or more semiconductor chips mounted on a circuitized surface of a substrate (e.g., a ceramic substrate or a plastic composite substrate). Such a semiconductor chip package is usually intended for mounting on a printed circuit card or board. In the case of a ball grid array (BGA) package, the chip carrier includes a second circuitized surface opposite the surface to which the chip is attached. This, in turn, is connected to the printed circuit card or board.
Chip carriers of this type provide a relatively high density of chip connections and are readily achieved by mounting one or more semiconductor chips on the circuitized surface of a chip carrier substrate in the so-called “flip chip” configuration.
Flip chip bonding is described by Charles G. Woychik and Richard C. Senger, “Joining Materials and Processes in Electronic Packaging” in PRINCIPLES OF ELECTRONIC PACKAGING, by Donald P. Seraphim, Ronald Lasky and Che-Yu Li, McGraw-Hill Book Company, New York, N.Y. (1988), at pages 577 to 619; and by Nicholas G. Koopman, Timothy C. Reiley, and Paul A. Totta, “Chip-To-Package Interconnections” in MICROELECTRONIC PACKAGING HANDBOOK, by Rao R. Tummala and Eugene Rymaszewski, Van Nostrand Reinhold, New York, N.Y. (1988), at pages 361 to 453.
Flip chips are small semiconductor dies having terminations all on one side of the entire face of the die in the form of a pattern of solder pads or bump contacts. These solder bumps are deposited on solder wettable terminals on the chip. Typically, the surface of the chip has been passivated or otherwise treated. In this way the use of a flip chip package allows full population area arrays of I/O. The flip chip derives its name from the practice of flipping or turning the chip over after manufacture, prior to attaching the chip to a matching substrate.
As described by Seraphim et al. and Tummala et al., an electronic circuit contains many individual electronic circuit components: thousands or even millions of individual resistors, capacitors, inductors, diodes, and transistors. These individual circuit components are interconnected to form the circuits. The individual circuits are interconnected to form functional units. Power and signal distribution are performed through these interconnections. The individual functional units require mechanical support and structural protection. The electrical circuits require electrical energy to function and the removal of thermal energy to remain functional. Microelectronic packages such as chips, modules, circuit cards, circuit boards, and combinations thereof are used to protect, house, cool, and interconnect circuit components and circuits.
In the flip chip configuration, the chip or chips are mounted active-side-down on solderable metal pads on the substrate using solder balls, a C4 connection, a gold bump, or a conductive epoxy.
Controlled collapse chip connection in flip chip technology has been successfully used for about 30 years for interconnecting high I/O count and area array solder bumps on the silicon chips to the base ceramic chip carriers (e.g., alumina carriers). In the C4 process, as distinguished from the flip chip process, the solder wettable terminals on the chip are surrounded by ball limiting metallurgy (BLM), and the matching footprint of solder wettable terminals on the card is surrounded by a solder mask. These structures act to limit the flow of molten solder during reflow.
Bonding can be used in an unpackaged configuration known in the art as direct chip attach (DCA): the direct connection of a chip to a card or board without an intermediate layer of packaging. The combination of a chip mounted on an intermediate carrier is usually described as the “first level package”. DCA can be a lower cost method of connecting a chip to a card, since the first level package is thereby eliminated.
For direct chip attach, individual IC chips are mounted on the cards or boards. The space between the mounted chip and the card or board is then filled with an epoxy resin. By this expedient, the standoff between the IC chip and the card or board is encapsulated with epoxy.
If a polymeric dielectric card or board is employed, the DCA process requires low temperature solder metallurgy. Moreover, direct chip attach, when used with an underfill, increases the fatigue resistance of the C4 solder interconnections to thermal cycling, acts as an alpha emission barrier to MOSFET memory chips, is a parallel thermal path for heat dissipation, and provides physical protection to the chips and C4 solder interconnections.
However, one problem encountered with the combination of DCA and C4 bonding is the difficulty of reworking the encapsulated package. In order to improve rework and to accommodate the CTE mismatches between the chip and the PWB, many prior art proposals have been developed to connect integrated circuit chips to printed wiring boards via an intermediate element. Often, chip carriers are interposed between the chip and the circuit board; the CTE of the chip carrier is itself chosen as some intermediate value to provide a reasonable match to both the chip and to the printed circuit board. The very large difference in CTE between the silicon device and the printed circuit board generally requires some intermediate device carrier. One such type of interconnection mounts the integrated circuit chip on a ceramic chip carrier or module, which module is mounted on a circuit board. One or more chips may be mounted on each device carrier or module, and one or more modules may be mounted on any given circuit board. In a particularly well known type of configuration, the integrated circuit chip is mounted onto a ceramic module by flip chip bonding wherein the I/O pads on the face of the chip are bonded to corresponding pads on the module. Such connections are formed by solder bumps or solder balls normally using solder reflow techniques. It is these connections that are referred to as C4 connections.
Most conventional single and multiple chip packages are typically co
Alcoe David J.
Johnson Eric A.
Reiss Matthew M.
Woychik Charles G.
Donovan Lincoln
Fraley Lawrence R.
International Business Machines - Corporation
Lee K.
Salzman & Levy
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