Apparatus for scan test of SRAM for microprocessors having full

Details Apparatus for scan test of SRAM for microprocessors having full Apparatus for scan test of SRAM for microprocessors having full

1998-11-05

2000-04-04

Wright, Norman Michael

Error detection/correction and fault detection/recovery

Data processing system error or fault handling

Reliability and availability

714 27, 714729, 714739, 714742, 710 14, G06F 1300, G06F 1126

Patent

active

06047386&

ABSTRACT:
An apparatus for allowing a RAM array within an SRAM to be tested via scan ATPG is disclosed. A first clocked flip-flop has a data input latched high, a scan-in input latched high, a clock input coupled to a signal source generating a periodic waveform, a scan-enable input coupled to a scan enable signal, and an output. The first flip-flop inverts the data input at the output when the scan enable signal is low, and places the scan-in input signal at the output when the scan enable signal is high. A second clocked flip-flop has a data input coupled to the output of the first flip-flop, a scan-in input latched high, a clock input coupled to the signal source, a scan enable input coupled to the scan enable signal, and an output. The second flip-flop inverts the data input at the output when the scan enable signal is low, and places the scan-in input signal at the output when the scan enable signal is high. An AND gate has a first input coupled to an inversion of the scan enable signal, a second input coupled to the output of the second flip-flop, and an output coupled to a write enable input to the SRAM.

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