Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch
Reexamination Certificate
2000-06-28
2001-06-05
Nelms, David (Department: 2818)
Static information storage and retrieval
Read/write circuit
Having particular data buffer or latch
C365S189110, C365S230080, C365S233100
Reexamination Certificate
active
06243302
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a double data rate (DDR) synchronous dynamic random access memory (SDRAM); and, more particularly, to a data output apparatus for outputting data stored in pipelatch circuits using common pull-up/pull-down lines which is controlled by a precharge unit.
DESCRIPTION OF THE PRIOR ART
Generally, synchronous dynamic random access memory (hereinafter, referred to as SDRAM) operating in synchronization with an external clock signal has been widely used to increase the speed thereof. SDRAM is synchronized with a rising edge of the external clock signal, but double data rate (DDR) SDRAM is synchronized with rising and falling edges of the external clock signal. Therefore, the DDR DRAM may increase operation speed twice as fast as SDRAMs without increasing the frequency of clock signal so that they are focused on the next generation DRAM devices. Furthermore, to process data continuously read out from memory cells, a plurality of pipeline latch circuits have been used in the SDRAMs.
In case where SDRAMs or DDR SDRAMs employing two-bit prefetch circuits, an output node of driver for driving an output buffer is shared with the prefetch circuits temporarily storing data read out from cells. Especially in 128 DDR SDRAMs, the output node is shared with 8 pipelatches. Therefore, when data are read out from one of them, the others act as a load with the increase of the access time.
Also, the output node of the pipelatches is made up of inverters having PMOS and NMOS transistors. In case of such a CMOS driver, the drivability of the PMOS transistor is a half of that of the NMOS transistor so that the PMOS transistor has to be twice as large as the NMOS transistor. As a result, the PMOS transistor has an amount of load twice as much as the NMOS transistor.
SUMMARY OF THE INVENTION
It is, therefore, an object of the present invention to provide an improved high speed DDR SDRAM with a reduced load in the pipelatch circuits.
In accordance with an aspect of the present invention, there is provided a synchronous memory device comprising: a plurality of pipelatch circuits storing data as pull-up and pull-down signals, transferring the stored data to pull-up and pull-down lines and producing initialization signals to initialize the pull-up and pull-down lines in response to a pipe count signal; common pull-up and pull-down lines coupled to the pull-up and pull-down lines in response to the pipe count signal and the initialization signals; initialization means for supplying a power supply to the pull-up and pull-down lines in response to a reset signal, the pipe count signal and the initialization signals; an output buffer outputting the data transferred by the common pull-up and pull-down lines; and a recharging mean for precharging the pull-up and pull-down lines and the common pull-up and pull-down lines in response to an output signal from the output buffer, wherein the common pull-up and pull-down lines is precharged to a ground voltage level.
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Han Jong-Hee
Yoon Min-Ho
Auduong Gene N.
Hyundai Electronics Industries Co,. Ltd.
Jacobson Price Holman & Stern PLLC
Nelms David
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