Signal generator with timing margin by using control signal...

Details Signal generator with timing margin by using control signal... Signal generator with timing margin by using control signal...

1999-12-17

2001-05-29

Nelms, David (Department: 2818)

Static information storage and retrieval

Addressing

Including particular address buffer or latch circuit...

C365S230060, C365S189050

Reexamination Certificate

active

06240041

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a semiconductor memory device; and, more particularly, to a semiconductor memory device capable of improving a timing margin in a logic circuit using a signal latch.
DESCRIPTION OF THE PRIOR ART
Generally, semiconductor memory devices have employed latch circuits for stability of signal transmission. An example having the latch circuits is shown in FIG.
1
A.
FIG. 1A
is a schematic block diagram illustrating a concept of signal transmission between an address signal generator and an Y-predecoder and
FIG. 1B
is a detail circuit diagram illustrating the Y-predecoder.
Referring to
FIGS. 1A and 1B
, first to fourth output signals gy
0
to gy
3
are output under the control of a control signal ypc. That is, input address signals are decoded in the Y-predecoder and then a bit line connected to a specific cell is selected. These output signals from the Y-predecoder are controlled by the control signal ypc from an external circuit.
FIG. 1C
is a waveform illustrating a signal generation with a true timing in FIG.
1
. As shown in
FIG. 1C
, when the control signal ypc is input within an exact margin for the input address signals iadd_p<
1
> and iadd_p<
2
>, the first output signal gy
0
is output in logically low level during the corresponding section (the second to fourth output signals gy
1
to gy
3
are continuously in a high level).
However, in the case where the control signal ypc is abnormally input at a rising or falling edge of the input address signal, an undesired decoding output signal is may be output, thereby deteriorating its reliability. As a result, this undesired decoding output signal makes cell data incorrect. To prevent this incorrect output data signal, it is possible to provide the timing margin for the control signal ypc in order to obtain the reliability in the signal processing with a false timing, as shown in FIG.
1
D. However, with the increase of the operation frequency in highly integrated circuits, this margin is subject to restriction.
SUMMARY OF THE INVENTION
It is, therefore, an object of the present invention to provide a memory device capable of transferring a signal at safety on a signal path having a latch circuit, without considering a separate timing margin.
It is another object of the present invention to provide an address signal generator making it stable to produce address signals in DRAMs, SDRAMs, or DDR SDRAMs.
In accordance with an aspect of the present invention, there is provided a semiconductor memory device comprising: a signal generator including a latch circuit, wherein the signal generator receives an external signal from an external circuit and latches the external signal in response to a control signal; and a pulse generating means for receiving outputs from the signal generator and for generating a pulse in response to the control signal.
The semiconductor memory device in accordance with the present invention further comprises a precharge means for precharging an output terminal of the signal generator in response to the control signal.
The signal generator in accordance with the present invention includes a CMOS inverter receiving the external signal and wherein the control signal enables the CMOS inverter.


REFERENCES:
patent: 5859799 (1999-01-01), Matsumoto et al.
patent: 6065092 (2000-05-01), Roy

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