Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2000-10-05
2003-12-09
Ton, David (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S727000, C714S729000
Reexamination Certificate
active
06662325
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to circuit testing, and, more particularly, to an apparatus for circuit testing that allows the circuit to be debugged while the circuit continues to perform normal circuit operations in the microprocessor.
BACKGROUND OF THE INVENTION
Advances in technology, such as the development of complex circuits including integrated circuits (ICs) and microprocessors, particularly surface mounted ICs and microprocessors have made traditional circuit testing methods extremely difficult. One prior art approach for testing complex circuits was to employ the Joint Test Action Group (JTAG) standard, which was developed by an international group of electronic manufacturers. The JTAG standard has been adopted by the Institute of Electrical and Electronic Engineers (IEEE) as IEEE Standard 1149.1-1990, IEEE Standard Test Access Port and Boundary-Scan Architecture (the “IEEE standard”), the contents of which are hereby incorporated in their entirety by reference.
In the prior art, the JTAG standard was typically used for boundary scan testing. Boundary scan testing allowed for testing based on a circuit's inputs and outputs, i.e., at the boundaries, but did not provide for testing of the core logic of a circuit or microprocessor.
The JTAG standard was occasionally used in the prior art to perform tests of the core logic of an IC. However, when the JTAG standard was used in the prior art to perform these tests, the tests were invasive because data was entered or outputted serially from one storage element to another. When the test data was entered or outputted serially from one storage element to another using prior art methods, the data originally contained in those storage elements was altered by the process. As a result, prior art testing of core logic using the JTAG standard typically required that the circuit, IC or microprocessor be taken out of normal operation within a system and run in a special test mode. These prior art methods resulted in the circuit not being tested during normal operation. Consequently, the data received did not test the circuit during actual system operation.
What is needed is a method and apparatus that allows for circuit debug while the circuit, IC or microprocessor remains on-line and continues to perform normal circuit operations.
SUMMARY OF THE INVENTION
In one embodiment of the invention, a circuit includes at least one functional unit. The functional unit includes a primary scan path and a shadow scan path. The shadow scan path receives data contained in the primary scan path and scans the data out of the functional unit for testing the operation of the circuit while the circuit continues its normal operations.
Thus, in accordance with the present invention, a series of secondary or “shadow” storage elements that duplicate, or “shadow”, the information in the core logic's primary storage elements are employed. These shadow storage elements are then connected together to form a separate, independently-addressable scan path (the secondary or “shadow” scan path). The information contained in the primary storage elements is then scanned out via the shadow scan path without altering the primary storage elements using special commands issued from a JTAG controller. This shadow scan system allows a circuit to remain operational while a snapshot of the core logic information is scanned out.
As discussed in more detail below, the apparatus of the present invention allows for access to the internal states of the microprocessor while the microprocessor continues to operate in a system. This is accomplished by capturing the contents of the functional primary storage elements into the shadow storage elements and then shifting the captured value out of the microprocessor without interrupting normal circuit operation. This is in direct contrast to prior art methods which either tested only at the boundaries, i.e., at the inputs and outputs of the circuit, or that required the microprocessor to be run in a special test mode. In addition, using the structure of the invention, real operating data is obtained from the microprocessor. This again is in direct contrast to the prior art methods where only data from special test mode operations could be obtained.
The structure of the present invention uses the JTAG standard and takes advantage of the separate JTAG clock (TCK) to manipulate the capture and shift operations of the shadow scan path using specially designed JTAG signals. In addition, using the structure of the invention, the shadow scan paths are not part of the microprocessor internal scan chain.
It is to be understood that both the foregoing general description and following detailed description are intended only to exemplify and explain the invention as claimed.
REFERENCES:
patent: 5054024 (1991-10-01), Whetsel
patent: 5056093 (1991-10-01), Whetsel
patent: 6060907 (2000-05-01), Vishwanthaiah
patent: 6131171 (2000-10-01), Whetsel
patent: 6185711 (2001-02-01), Leung et al.
patent: 6380724 (2002-04-01), Mahurin et al.
patent: 6496030 (2002-12-01), Kaneko
Gunnison McKay & Hodgson, L.L.P.
McKay Philip J.
Sun Microsystems Inc.
Ton David
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