Apparatus for analyzing a failure in a semiconductor wafer and m

Details Apparatus for analyzing a failure in a semiconductor wafer and m Apparatus for analyzing a failure in a semiconductor wafer and m

1996-03-21

1998-12-01

Nguyen, Viet Q.

Static information storage and retrieval

Read/write circuit

Bad bit

371 48, 371 211, H01L 2166

Patent

active

058448500

ABSTRACT:
Data containing defect position coordinates obtained based on the result of physical inspection of a foreign material, a defect and the like at a surface of a semiconductor wafer by a defect inspecting apparatus is stored in storage means. Data of physical position coordinates obtained based on fail bit data from a tester is stored in storage means. Data indicating an additional failure region is produced by additional failure region estimating means based on the fail bit data, and is stored in storage means. Collating means produces data of corrected physical position coordinates by adding the data of limitation by failure mode stored in storage means to the data of physical position coordinates stored in storage means, and collates the data of corrected physical position coordinates with data of defect position coordinates stored in storage means. Accordingly, accuracy in collation is improved, and therefore, a failure can be analyzed even if the failure is not caused by a defect located at an address of the failure obtained by the fail bit data but by a defect relating to the defect located at the address of a failure. As a result, accuracy in estimation is improved.

REFERENCES:
patent: 4985927 (1991-01-01), Norwood et al.
patent: 5018212 (1991-05-01), Manns et al.
patent: 5038048 (1991-08-01), Maeda et al.
patent: 5404410 (1995-04-01), Tojo et al.
"Expert System for Semiconductor Failure Analysis Using ARES/DIAG", by H. Nakawatase et al., Toshiba Review, 1994, vol. 49, No. 8, pp. 563-566.
"In-Line Monitoring Technology Using Memory Failure Analysis Expert System" by Tohru Tsujide, 1993.

Affiliated with

Also associated with

Rating

Apparatus for analyzing a failure in a semiconductor wafer and m does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Apparatus for analyzing a failure in a semiconductor wafer and m, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Apparatus for analyzing a failure in a semiconductor wafer and m will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2400873