Apparatus and method for testing and debugging an integrated...

Details Apparatus and method for testing and debugging an integrated... Apparatus and method for testing and debugging an integrated...

2005-05-17

2009-02-24

Trimmings, John P. (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S025000, C714S030000, C714S031000, C714S039000, C714S732000, C714S733000, C714S734000, C710S317000

Reexamination Certificate

active

07496812

ABSTRACT:
An interface that communicates with first and second interface modules, an analyzer and an integrated circuit comprises a first path from the first and second interface modules and the analyzer to the integrated circuit. The first path includes a first serializer that serializes at least one of first control data and/or test data from at least one of the first and/or second interface modules. A second path from the integrated circuit to the first and second interface modules and the analyzer includes a high speed deserializer that deserializes serial data containing at least one of test result data and/or second control data from the integrated circuit. A frame sync module synchronizes data from the high speed deserializer to identify frames. The high speed deserializer outputs the second control data to at least one of the first and/or second interface modules. The frame sync module outputs the frames to the analyzer.

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IEEE Standard 1149.1, IEEE Standard Test Access Port and Boundary-Scan Architecture, 2001, 208 pages.

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